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Fix 'ret long' to return the high and lo parts in the right registers. This

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fixes crafty and probably others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23167 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-08-31 01:34:29 +00:00
parent fe75a2836a
commit 7a49fdcd11
1 changed files with 7 additions and 9 deletions
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10
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@@ -1569,7 +1569,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
case ISD::RET: { case ISD::RET: {
SDOperand Chain = Select(N->getOperand(0)); // Token chain. SDOperand Chain = Select(N->getOperand(0)); // Token chain.
if (N->getNumOperands() > 1) { if (N->getNumOperands() == 2) {
SDOperand Val = Select(N->getOperand(1)); SDOperand Val = Select(N->getOperand(1));
if (N->getOperand(1).getValueType() == MVT::i32) { if (N->getOperand(1).getValueType() == MVT::i32) {
Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val); Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
@@ -1577,14 +1577,12 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
assert(MVT::isFloatingPoint(N->getOperand(1).getValueType())); assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val); Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
} }
} else if (N->getNumOperands() > 1) {
if (N->getNumOperands() > 2) {
assert(N->getOperand(1).getValueType() == MVT::i32 && assert(N->getOperand(1).getValueType() == MVT::i32 &&
N->getOperand(2).getValueType() == MVT::i32 && N->getOperand(2).getValueType() == MVT::i32 &&
N->getNumOperands() == 3 && "Unknown two-register ret value!"); N->getNumOperands() == 3 && "Unknown two-register ret value!");
Val = Select(N->getOperand(2)); Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Select(N->getOperand(1)));
Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val); Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Select(N->getOperand(2)));
}
} }
// Finally, select this to a blr (return) instruction. // Finally, select this to a blr (return) instruction.