6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-01 00:33:09 +00:00
Code Issues Projects Releases Wiki Activity

IntegerRegSize is always 8 for sparc

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5961 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-04-26 19:44:35 +00:00
parent 38f8c4520f
commit 7a5adc3ac0
2 changed files with 3 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/SparcV9/SparcV9InstrInfo.cpp
View File

@ -441,9 +441,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
assert(isValidConstant && "Unrecognized constant");
if (opSize > destSize ||
(val->getType()->isSigned()
&& destSize < target.getTargetData().getIntegerRegSize()))
if (opSize > destSize || (val->getType()->isSigned() && destSize < 8))
{ // operand is larger than dest,
// OR both are equal but smaller than the full register size
// AND operand is signed, so it may have extra sign bits:

5
lib/Target/SparcV9/SparcV9InstrSelection.cpp
View File

@ -758,8 +758,7 @@ CreateShiftInstructions(const TargetMachine& target,
//
Value* shiftDest = destVal;
unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
if ((shiftOpCode == SLL || shiftOpCode == SLLX)
&& opSize < target.getTargetData().getIntegerRegSize())
if ((shiftOpCode == SLL || shiftOpCode == SLLX) && opSize < 8)
{ // put SLL result into a temporary
shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
mcfi.addTemp(shiftDest);
@ -2305,7 +2304,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
.addReg(dest, MOTy::Def);
mvec.push_back(M);
}
else if (destSize < target.getTargetData().getIntegerRegSize())
else if (destSize < 8)
assert(0 && "Unsupported type size: 32 < size < 64 bits");
}
}