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https://github.com/c64scene-ar/llvm-6502.git
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Add bunch of FP instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76019 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
23eff5c75a
commit
7aa03ac827
@ -47,6 +47,7 @@ include "SystemZCallingConv.td"
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//===----------------------------------------------------------------------===//
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include "SystemZInstrInfo.td"
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include "SystemZInstrFP.td"
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def SystemZInstrInfo : InstrInfo {}
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156
lib/Target/SystemZ/SystemZInstrFP.td
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156
lib/Target/SystemZ/SystemZInstrFP.td
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@ -0,0 +1,156 @@
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//===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the SystemZ (binary) floating point instructions in
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// TableGen format.
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//
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//===----------------------------------------------------------------------===//
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// FIXME: multiclassify!
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//===----------------------------------------------------------------------===//
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// Move Instructions
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let neverHasSideEffects = 1 in {
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def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
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"ler\t{$dst, $src}",
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[]>;
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def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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"ldr\t{$dst, $src}",
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[]>;
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}
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let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
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def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
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"le\t{$dst, $src}",
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[(set FP32:$dst, (load rriaddr12:$src))]>;
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def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
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"ley\t{$dst, $src}",
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[(set FP32:$dst, (load rriaddr:$src))]>;
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def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
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"ld\t{$dst, $src}",
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[(set FP64:$dst, (load rriaddr12:$src))]>;
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def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
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"ldy\t{$dst, $src}",
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[(set FP64:$dst, (load rriaddr:$src))]>;
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}
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def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
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"ste\t{$src, $dst}",
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[(store FP32:$src, rriaddr12:$dst)]>;
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def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
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"stey\t{$src, $dst}",
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[(store FP32:$src, rriaddr:$dst)]>;
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def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
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"std\t{$src, $dst}",
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[(store FP64:$src, rriaddr12:$dst)]>;
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def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
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"stdy\t{$src, $dst}",
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[(store FP64:$src, rriaddr:$dst)]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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let isTwoAddress = 1 in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"aebr\t{$dst, $src2}",
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[(set FP32:$dst, (fadd FP32:$src1, FP32:$src2))]>;
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def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"adbr\t{$dst, $src2}",
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[(set FP64:$dst, (fadd FP64:$src1, FP64:$src2))]>;
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}
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def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
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"aeb\t{$dst, $src2}",
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[(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2)))]>;
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def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
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"adb\t{$dst, $src2}",
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[(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2)))]>;
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def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"sebr\t{$dst, $src2}",
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[(set FP32:$dst, (fsub FP32:$src1, FP32:$src2))]>;
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def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"sdbr\t{$dst, $src2}",
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[(set FP64:$dst, (fsub FP64:$src1, FP64:$src2))]>;
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def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
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"seb\t{$dst, $src2}",
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[(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2)))]>;
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def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
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"sdb\t{$dst, $src2}",
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[(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2)))]>;
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let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
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def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"meebr\t{$dst, $src2}",
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[(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
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def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"mdbr\t{$dst, $src2}",
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[(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
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}
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def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
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"meeb\t{$dst, $src2}",
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[(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>;
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def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
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"mdb\t{$dst, $src2}",
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[(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>;
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def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"debr\t{$dst, $src2}",
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[(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
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def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"ddbr\t{$dst, $src2}",
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[(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
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def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
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"deb\t{$dst, $src2}",
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[(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>;
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def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
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"ddb\t{$dst, $src2}",
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[(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>;
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} // isTwoAddress = 1
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def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
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"ledbr\t{$dst, $src}",
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[(set FP32:$dst, (fround FP64:$src))]>;
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def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
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"cefbr\t{$dst, $src}",
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[(set FP32:$dst, (sint_to_fp GR32:$src))]>;
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def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
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"cdgbr\t{$dst, $src}",
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[(set FP64:$dst, (sint_to_fp GR64:$src))]>;
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//===----------------------------------------------------------------------===//
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// Test instructions (like AND but do not produce any result)
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// Integer comparisons
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let Defs = [PSW] in {
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def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
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"cebr\t$src1, $src2",
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[(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
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def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
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"cdbr\t$src1, $src2",
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[(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
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def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2),
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"ceb\t$src1, $src2",
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[(SystemZcmp FP32:$src1, (load rriaddr:$src2)),
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(implicit PSW)]>;
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def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
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"cdb\t$src1, $src2",
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[(SystemZcmp FP64:$src1, (load rriaddr:$src2)),
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(implicit PSW)]>;
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} // Defs = [PSW]
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@ -121,6 +121,10 @@ bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::GR128RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::FP32RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::FP64RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg);
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} else {
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return false;
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}
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@ -156,6 +160,8 @@ SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
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case SystemZ::MOV64rr:
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case SystemZ::MOV64rrP:
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case SystemZ::MOV128rr:
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case SystemZ::FMOV32rr:
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case SystemZ::FMOV64rr:
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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