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Switch over to TableGen generated register file description

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-08-03 15:48:14 +00:00
parent 762fb5f704
commit 7ad3e063f5
4 changed files with 28 additions and 274 deletions
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17
lib/Target/X86/Makefile
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@ -2,3 +2,20 @@ LEVEL = ../../..
LIBRARYNAME = x86
include $(LEVEL)/Makefile.common
# Make sure that tblgen is run, first thing.
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc
X86GenRegisterNames.inc: $(wildcard *.td) $(TBLGEN)
$(TBLGEN) X86.td -gen-register-enums -o $@
X86GenRegisterInfo.h.inc: $(wildcard *.td) $(TBLGEN)
$(TBLGEN) X86.td -gen-register-desc-header -o $@
X86GenRegisterInfo.inc: $(wildcard *.td) $(TBLGEN)
$(TBLGEN) X86.td -gen-register-desc -o $@
clean::
$(VERB) rm -f *.inc

117
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -24,6 +24,9 @@ namespace {
cl::desc("Disable frame pointer elimination optimization"));
}
X86RegisterInfo::X86RegisterInfo()
: X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
static unsigned getIdx(const TargetRegisterClass *RC) {
switch (RC->getSize()) {
default: assert(0 && "Invalid data size!");
@ -66,14 +69,6 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MBBI = MBB.insert(MBBI, MI)+1;
}
const unsigned* X86RegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
};
return CalleeSaveRegs;
}
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
@ -249,103 +244,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
}
}
//===----------------------------------------------------------------------===//
// Register Class Implementation Code
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// 8 Bit Integer Registers
//
namespace {
const unsigned ByteRegClassRegs[] = {
X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, X86::DH, X86::BH,
};
TargetRegisterClass X86ByteRegisterClassInstance(1, 1, ByteRegClassRegs,
ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
//===----------------------------------------------------------------------===//
// 16 Bit Integer Registers
//
const unsigned ShortRegClassRegs[] = {
X86::AX, X86::CX, X86::DX, X86::BX, X86::SI, X86::DI, X86::BP, X86::SP
};
struct R16CL : public TargetRegisterClass {
R16CL():TargetRegisterClass(2, 2, ShortRegClassRegs, ShortRegClassRegs+8) {}
iterator allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
return end()-2; // Don't allocate SP or BP
else
return end()-1; // Don't allocate SP
}
} X86ShortRegisterClassInstance;
//===----------------------------------------------------------------------===//
// 32 Bit Integer Registers
//
const unsigned IntRegClassRegs[] = {
X86::EAX, X86::ECX, X86::EDX, X86::EBX,
X86::ESI, X86::EDI, X86::EBP, X86::ESP
};
struct R32CL : public TargetRegisterClass {
R32CL() : TargetRegisterClass(4, 4, IntRegClassRegs, IntRegClassRegs+8) {}
iterator allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
return end()-2; // Don't allocate ESP or EBP
else
return end()-1; // Don't allocate ESP
}
} X86IntRegisterClassInstance;
//===----------------------------------------------------------------------===//
// Pseudo Floating Point Registers
//
const unsigned PFPRegClassRegs[] = {
#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
#include "X86RegisterInfo.def"
};
TargetRegisterClass X86FPRegisterClassInstance(10, 4, PFPRegClassRegs,
PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0]));
//===----------------------------------------------------------------------===//
// Register class array...
//
const TargetRegisterClass * const X86RegClasses[] = {
&X86ByteRegisterClassInstance,
&X86ShortRegisterClassInstance,
&X86IntRegisterClassInstance,
&X86FPRegisterClassInstance,
};
}
// Create static lists to contain register alias sets...
#define ALIASLIST(NAME, ...) \
static const unsigned NAME[] = { __VA_ARGS__ };
#include "X86RegisterInfo.def"
// X86Regs - Turn the X86RegisterInfo.def file into a bunch of register
// descriptors
//
static const MRegisterDesc X86Regs[] = {
#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
{ NAME, ALIAS_SET, FLAGS, TSFLAGS },
#include "X86RegisterInfo.def"
};
X86RegisterInfo::X86RegisterInfo()
: MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0]),
X86RegClasses,
X86RegClasses+sizeof(X86RegClasses)/sizeof(X86RegClasses[0]),
X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {
}
#include "X86GenRegisterInfo.inc"
const TargetRegisterClass*
X86RegisterInfo::getRegClassForType(const Type* Ty) const {
@ -355,14 +254,14 @@ X86RegisterInfo::getRegClassForType(const Type* Ty) const {
default: assert(0 && "Invalid type to getClass!");
case Type::BoolTyID:
case Type::SByteTyID:
case Type::UByteTyID: return &X86ByteRegisterClassInstance;
case Type::UByteTyID: return &r8Instance;
case Type::ShortTyID:
case Type::UShortTyID: return &X86ShortRegisterClassInstance;
case Type::UShortTyID: return &r16Instance;
case Type::IntTyID:
case Type::UIntTyID:
case Type::PointerTyID: return &X86IntRegisterClassInstance;
case Type::PointerTyID: return &r32Instance;
case Type::FloatTyID:
case Type::DoubleTyID: return &X86FPRegisterClassInstance;
case Type::DoubleTyID: return &rFPInstance;
}
}

161
lib/Target/X86/X86RegisterInfo.def
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@ -1,161 +0,0 @@
//===-- X86RegisterInfo.def - X86 Register Information ----------*- C++ -*-===//
//
// This file describes all of the registers that the X86 backend uses. It relies
// on an external 'R' macro being defined that takes the arguments specified
// below, and is used to make all of the information relevant to registers be in
// one place.
//
//===----------------------------------------------------------------------===//
// NOTE: No include guards desired
#ifndef R
#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
#ifndef R8
#define R8(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
#ifndef R16
#define R16(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
#ifndef R32
#define R32(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
// Pseudo Floating Point registers
#ifndef PFP
#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
// Floating Point Stack registers
#ifndef FPS
#define FPS(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
// Arguments passed into the R macros
// #1: Enum Name - This ends up being a symbol in the X86 namespace
// #2: Register name - The name of the register as used by the gnu assembler
// #3: Register Flags - A bitfield of flags or'd together from the
// MRegisterInfo.h file.
// #4: Target Specific Flags - Another bitfield containing X86 specific flags
// as necessary.
// #5: Alias set for registers aliased to this register (sets defined below).
// The first register must always be a 'noop' register for all backends. This
// is used as the destination register for instructions that do not produce a
// value. Some frontends may use this as an operand register to mean special
// things, for example, the Sparc backend uses R#0 to mean %g0 which always
// PRODUCES the value 0.
//
// The X86 backend uses this value as an operand register only in memory
// references where it means that there is no base or index register.
//
R(NoReg,"none", 0, 0, 0/*noalias*/)
// 32 bit registers, ordered as the processor does...
R32(EAX, "EAX", MVT::i32, 0, A_EAX)
R32(ECX, "ECX", MVT::i32, 0, A_ECX)
R32(EDX, "EDX", MVT::i32, 0, A_EDX)
R32(EBX, "EBX", MVT::i32, 0, A_EBX)
R32(ESP, "ESP", MVT::i32, 0, A_ESP)
R32(EBP, "EBP", MVT::i32, 0, A_EBP)
R32(ESI, "ESI", MVT::i32, 0, A_ESI)
R32(EDI, "EDI", MVT::i32, 0, A_EDI)
// 16 bit registers, aliased with the corresponding 32 bit registers above
R16( AX, "AX" , MVT::i16, 0, A_AX)
R16( CX, "CX" , MVT::i16, 0, A_CX)
R16( DX, "DX" , MVT::i16, 0, A_DX)
R16( BX, "BX" , MVT::i16, 0, A_BX)
R16( SP, "SP" , MVT::i16, 0, A_SP)
R16( BP, "BP" , MVT::i16, 0, A_BP)
R16( SI, "SI" , MVT::i16, 0, A_SI)
R16( DI, "DI" , MVT::i16, 0, A_DI)
// 8 bit registers aliased with registers above as well
R8 ( AL, "AL" , MVT::i8 , 0, A_AL)
R8 ( CL, "CL" , MVT::i8 , 0, A_CL)
R8 ( DL, "DL" , MVT::i8 , 0, A_DL)
R8 ( BL, "BL" , MVT::i8 , 0, A_BL)
R8 ( AH, "AH" , MVT::i8 , 0, A_AH)
R8 ( CH, "CH" , MVT::i8 , 0, A_CH)
R8 ( DH, "DH" , MVT::i8 , 0, A_DH)
R8 ( BH, "BH" , MVT::i8 , 0, A_BH)
// Pseudo Floating Point Registers
PFP(FP0, "FP0", MVT::f80 , 0, 0 /*noalias*/)
PFP(FP1, "FP1", MVT::f80 , 0, 0 /*noalias*/)
PFP(FP2, "FP2", MVT::f80 , 0, 0 /*noalias*/)
PFP(FP3, "FP3", MVT::f80 , 0, 0 /*noalias*/)
PFP(FP4, "FP4", MVT::f80 , 0, 0 /*noalias*/)
PFP(FP5, "FP5", MVT::f80 , 0, 0 /*noalias*/)
PFP(FP6, "FP6", MVT::f80 , 0, 0 /*noalias*/)
// Floating point stack registers
FPS(ST0, "ST(0)", MVT::f80, 0, 0)
FPS(ST1, "ST(1)", MVT::f80, 0, 0)
FPS(ST2, "ST(2)", MVT::f80, 0, 0)
FPS(ST3, "ST(3)", MVT::f80, 0, 0)
FPS(ST4, "ST(4)", MVT::f80, 0, 0)
FPS(ST5, "ST(5)", MVT::f80, 0, 0)
FPS(ST6, "ST(6)", MVT::f80, 0, 0)
FPS(ST7, "ST(7)", MVT::f80, 0, 0)
// Flags, Segment registers, etc...
// This is a slimy hack to make it possible to say that flags are clobbered...
// Ideally we'd model instructions based on which particular flag(s) they
// could clobber.
R(EFLAGS, "EFLAGS", MVT::i16, 0, 0 /*noalias*/)
//===----------------------------------------------------------------------===//
// Register alias set handling...
//
// Macro to handle definitions of alias sets that registers use...
#ifndef ALIASLIST
#define ALIASLIST(NAME, ...)
#endif
ALIASLIST(A_EAX , X86::AX, X86::AH, X86::AL, 0)
ALIASLIST(A_ECX , X86::CX, X86::CH, X86::CL, 0)
ALIASLIST(A_EDX , X86::DX, X86::DH, X86::DL, 0)
ALIASLIST(A_EBX , X86::BX, X86::BH, X86::BL, 0)
ALIASLIST(A_ESP , X86::SP, 0)
ALIASLIST(A_EBP , X86::BP, 0)
ALIASLIST(A_ESI , X86::SI, 0)
ALIASLIST(A_EDI , X86::DI, 0)
ALIASLIST(A_AX , X86::EAX, X86::AH, X86::AL, 0)
ALIASLIST(A_CX , X86::ECX, X86::CH, X86::CL, 0)
ALIASLIST(A_DX , X86::EDX, X86::DH, X86::DL, 0)
ALIASLIST(A_BX , X86::EBX, X86::BH, X86::BL, 0)
ALIASLIST(A_SP , X86::ESP, 0)
ALIASLIST(A_BP , X86::EBP, 0)
ALIASLIST(A_SI , X86::ESI, 0)
ALIASLIST(A_DI , X86::EDI, 0)
ALIASLIST(A_AL , X86::EAX, X86::AX, 0)
ALIASLIST(A_CL , X86::ECX, X86::CX, 0)
ALIASLIST(A_DL , X86::EDX, X86::DX, 0)
ALIASLIST(A_BL , X86::EBX, X86::BX, 0)
ALIASLIST(A_AH , X86::EAX, X86::AX, 0)
ALIASLIST(A_CH , X86::ECX, X86::CX, 0)
ALIASLIST(A_DH , X86::EDX, X86::DX, 0)
ALIASLIST(A_BH , X86::EBX, X86::BX, 0)
#undef ALIASLIST
// We are now done with the R* macros
#undef R
#undef R8
#undef R16
#undef R32
#undef PFP
#undef FPS

7
lib/Target/X86/X86RegisterInfo.h
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@ -11,11 +11,10 @@
class Type;
struct X86RegisterInfo : public MRegisterInfo {
#include "X86GenRegisterInfo.h.inc"
struct X86RegisterInfo : public X86GenRegisterInfo {
X86RegisterInfo();
const unsigned* getCalleeSaveRegs() const;
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
/// Code Generation virtual methods...