diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h
index 0694caa346a..ee1ed0779be 100644
--- a/include/llvm/CodeGen/DFAPacketizer.h
+++ b/include/llvm/CodeGen/DFAPacketizer.h
@@ -36,6 +36,7 @@ class MachineInstr;
 class MachineLoopInfo;
 class MachineDominatorTree;
 class InstrItineraryData;
+class ScheduleDAGInstrs;
 class SUnit;
 
 class DFAPacketizer {
@@ -91,7 +92,7 @@ class VLIWPacketizerList {
   const TargetInstrInfo *TII;
 
   // Encapsulate data types not exposed to the target interface.
-  void *SchedulerImpl;
+  ScheduleDAGInstrs *SchedulerImpl;
 
 protected:
   // Vector of instructions assigned to the current packet.
diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h
index 5b1cbaa5ebb..4c6b74df2ae 100644
--- a/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -245,15 +245,16 @@ namespace llvm {
     /// end - Return an iterator to the bottom of the current scheduling region.
     MachineBasicBlock::iterator end() const { return End; }
 
-    /// NewSUnit - Creates a new SUnit and return a ptr to it.
+    /// newSUnit - Creates a new SUnit and return a ptr to it.
     SUnit *newSUnit(MachineInstr *MI);
 
+    /// getSUnit - Return an existing SUnit for this MI, or NULL.
+    SUnit *getSUnit(MachineInstr *MI) const;
+
     /// startBlock - Prepare to perform scheduling in the given block.
-    ///
     virtual void startBlock(MachineBasicBlock *BB);
 
     /// finishBlock - Clean up after scheduling in the given block.
-    ///
     virtual void finishBlock();
 
     /// Initialize the scheduler state for the next scheduling region.
@@ -304,13 +305,6 @@ namespace llvm {
     virtual std::string getDAGName() const;
 
   protected:
-    SUnit *getSUnit(MachineInstr *MI) const {
-      DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
-      if (I == MISUnitMap.end())
-        return 0;
-      return I->second;
-    }
-
     void initSUnits();
     void addPhysRegDataDeps(SUnit *SU, const MachineOperand &MO);
     void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
@@ -322,8 +316,7 @@ namespace llvm {
     }
   };
 
-  /// NewSUnit - Creates a new SUnit and return a ptr to it.
-  ///
+  /// newSUnit - Creates a new SUnit and return a ptr to it.
   inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
 #ifndef NDEBUG
     const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
@@ -334,6 +327,14 @@ namespace llvm {
     SUnits.back().OrigNode = &SUnits.back();
     return &SUnits.back();
   }
+
+  /// getSUnit - Return an existing SUnit for this MI, or NULL.
+  inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
+    DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
+    if (I == MISUnitMap.end())
+      return 0;
+    return I->second;
+  }
 } // namespace llvm
 
 #endif
diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp
index 3d178c76f97..5ff641c7c84 100644
--- a/lib/CodeGen/DFAPacketizer.cpp
+++ b/lib/CodeGen/DFAPacketizer.cpp
@@ -103,9 +103,6 @@ void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
 namespace {
 // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
 // Schedule method to build the dependence graph.
-//
-// ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so we have to reference it as
-// an opaque pointer in VLIWPacketizerList.
 class DefaultVLIWScheduler : public ScheduleDAGInstrs {
 public:
   DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
@@ -137,7 +134,7 @@ VLIWPacketizerList::VLIWPacketizerList(
 
 // VLIWPacketizerList Dtor
 VLIWPacketizerList::~VLIWPacketizerList() {
-  delete (DefaultVLIWScheduler *)SchedulerImpl;
+  delete SchedulerImpl;
   delete ResourceTracker;
 }
 
@@ -184,20 +181,15 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
                                       MachineBasicBlock::iterator BeginItr,
                                       MachineBasicBlock::iterator EndItr) {
-  DefaultVLIWScheduler *Scheduler = (DefaultVLIWScheduler *)SchedulerImpl;
-  Scheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size());
-  Scheduler->schedule();
-  Scheduler->exitRegion();
+  assert(MBB->end() == EndItr && "Bad EndIndex");
+
+  SchedulerImpl->enterRegion(MBB, BeginItr, EndItr, MBB->size());
+
+  // Build the DAG without reordering instructions.
+  SchedulerImpl->schedule();
 
   // Remember scheduling units.
-  SUnits = Scheduler->SUnits;
-
-  // Generate MI -> SU map.
-  std::map <MachineInstr*, SUnit*> MIToSUnit;
-  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
-    SUnit *SU = &SUnits[i];
-    MIToSUnit[SU->getInstr()] = SU;
-  }
+  SUnits = SchedulerImpl->SUnits;
 
   // The main packetizer loop.
   for (; BeginItr != EndItr; ++BeginItr) {
@@ -213,7 +205,7 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
       continue;
     }
 
-    SUnit *SUI = MIToSUnit[MI];
+    SUnit *SUI = SchedulerImpl->getSUnit(MI);
     assert(SUI && "Missing SUnit Info!");
 
     // Ask DFA if machine resource is available for MI.
@@ -223,7 +215,7 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
       for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
            VE = CurrentPacketMIs.end(); VI != VE; ++VI) {
         MachineInstr *MJ = *VI;
-        SUnit *SUJ = MIToSUnit[MJ];
+        SUnit *SUJ = SchedulerImpl->getSUnit(MJ);
         assert(SUJ && "Missing SUnit Info!");
 
         // Is it legal to packetize SUI and SUJ together.
@@ -247,4 +239,6 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
 
   // End any packet left behind.
   endPacket(MBB, EndItr);
+
+  SchedulerImpl->exitRegion();
 }