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[X86] Reordered lowerVectorShuffleAsBitMask before lowerVectorShuffleAsBlend. NFCI.
Allows us to show diffs for D11518 more clearly git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243264 91177308-0d34-0410-b5e6-96231b3b80d8
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Simon Pilgrim committed
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@@ -6471,6 +6471,92 @@ static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
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return DAG.getConstant(Imm, DL, MVT::i8);
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return DAG.getConstant(Imm, DL, MVT::i8);
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}
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}
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/// \brief Compute whether each element of a shuffle is zeroable.
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///
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/// A "zeroable" vector shuffle element is one which can be lowered to zero.
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/// Either it is an undef element in the shuffle mask, the element of the input
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/// referenced is undef, or the element of the input referenced is known to be
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/// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
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/// as many lanes with this technique as possible to simplify the remaining
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/// shuffle.
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static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
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SDValue V1, SDValue V2) {
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SmallBitVector Zeroable(Mask.size(), false);
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while (V1.getOpcode() == ISD::BITCAST)
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V1 = V1->getOperand(0);
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while (V2.getOpcode() == ISD::BITCAST)
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V2 = V2->getOperand(0);
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bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
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bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
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for (int i = 0, Size = Mask.size(); i < Size; ++i) {
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int M = Mask[i];
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// Handle the easy cases.
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if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
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Zeroable[i] = true;
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continue;
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}
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// If this is an index into a build_vector node (which has the same number
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// of elements), dig out the input value and use it.
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SDValue V = M < Size ? V1 : V2;
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if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
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continue;
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SDValue Input = V.getOperand(M % Size);
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// The UNDEF opcode check really should be dead code here, but not quite
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// worth asserting on (it isn't invalid, just unexpected).
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if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
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Zeroable[i] = true;
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}
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return Zeroable;
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}
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/// \brief Try to emit a bitmask instruction for a shuffle.
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///
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/// This handles cases where we can model a blend exactly as a bitmask due to
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/// one of the inputs being zeroable.
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static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
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SDValue V2, ArrayRef<int> Mask,
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SelectionDAG &DAG) {
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MVT EltVT = VT.getScalarType();
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int NumEltBits = EltVT.getSizeInBits();
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MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
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SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
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SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
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IntEltVT);
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if (EltVT.isFloatingPoint()) {
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Zero = DAG.getBitcast(EltVT, Zero);
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AllOnes = DAG.getBitcast(EltVT, AllOnes);
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}
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SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
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SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
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SDValue V;
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for (int i = 0, Size = Mask.size(); i < Size; ++i) {
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if (Zeroable[i])
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continue;
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if (Mask[i] % Size != i)
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return SDValue(); // Not a blend.
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if (!V)
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V = Mask[i] < Size ? V1 : V2;
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else if (V != (Mask[i] < Size ? V1 : V2))
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return SDValue(); // Can only let one input through the mask.
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VMaskOps[i] = AllOnes;
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}
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if (!V)
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return SDValue(); // No non-zeroable elements!
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SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
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V = DAG.getNode(VT.isFloatingPoint()
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? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
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DL, VT, V, VMask);
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return V;
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}
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/// \brief Try to emit a blend instruction for a shuffle using bit math.
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/// \brief Try to emit a blend instruction for a shuffle using bit math.
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///
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///
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/// This is used as a fallback approach when first class blend instructions are
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/// This is used as a fallback approach when first class blend instructions are
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@@ -6834,92 +6920,6 @@ static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
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DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
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DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
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}
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}
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/// \brief Compute whether each element of a shuffle is zeroable.
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///
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/// A "zeroable" vector shuffle element is one which can be lowered to zero.
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/// Either it is an undef element in the shuffle mask, the element of the input
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/// referenced is undef, or the element of the input referenced is known to be
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/// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
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/// as many lanes with this technique as possible to simplify the remaining
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/// shuffle.
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static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
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SDValue V1, SDValue V2) {
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SmallBitVector Zeroable(Mask.size(), false);
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while (V1.getOpcode() == ISD::BITCAST)
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V1 = V1->getOperand(0);
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while (V2.getOpcode() == ISD::BITCAST)
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V2 = V2->getOperand(0);
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bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
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bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
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for (int i = 0, Size = Mask.size(); i < Size; ++i) {
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int M = Mask[i];
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// Handle the easy cases.
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if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
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Zeroable[i] = true;
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continue;
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}
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// If this is an index into a build_vector node (which has the same number
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// of elements), dig out the input value and use it.
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SDValue V = M < Size ? V1 : V2;
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if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
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continue;
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SDValue Input = V.getOperand(M % Size);
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// The UNDEF opcode check really should be dead code here, but not quite
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// worth asserting on (it isn't invalid, just unexpected).
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if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
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Zeroable[i] = true;
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}
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return Zeroable;
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}
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/// \brief Try to emit a bitmask instruction for a shuffle.
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///
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/// This handles cases where we can model a blend exactly as a bitmask due to
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/// one of the inputs being zeroable.
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static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
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SDValue V2, ArrayRef<int> Mask,
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SelectionDAG &DAG) {
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MVT EltVT = VT.getScalarType();
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int NumEltBits = EltVT.getSizeInBits();
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MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
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SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
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SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
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IntEltVT);
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if (EltVT.isFloatingPoint()) {
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Zero = DAG.getBitcast(EltVT, Zero);
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AllOnes = DAG.getBitcast(EltVT, AllOnes);
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}
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SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
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SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
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SDValue V;
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for (int i = 0, Size = Mask.size(); i < Size; ++i) {
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if (Zeroable[i])
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continue;
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if (Mask[i] % Size != i)
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return SDValue(); // Not a blend.
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if (!V)
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V = Mask[i] < Size ? V1 : V2;
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else if (V != (Mask[i] < Size ? V1 : V2))
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return SDValue(); // Can only let one input through the mask.
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VMaskOps[i] = AllOnes;
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}
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if (!V)
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return SDValue(); // No non-zeroable elements!
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SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
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V = DAG.getNode(VT.isFloatingPoint()
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? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
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DL, VT, V, VMask);
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return V;
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}
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/// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
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/// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
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///
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///
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/// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
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/// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
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