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Add a new form of MCOperand, for representing sub-instructions. This is intended for supporting bundles through the MC layer, rather than lowering them pre-MC as we currently do for Thumb2 IT blocks. Since these sub-instruction operands hold pointers to the sub-instructions, it is the responsibility of the target's AsmPrinter to provide storage for them for the duration of the EmitInstruction() call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148492 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -25,6 +25,7 @@ class raw_ostream;
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class MCAsmInfo;
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class MCInstPrinter;
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class MCExpr;
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class MCInst;
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/// MCOperand - Instances of this class represent operands of the MCInst class.
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/// This is a simple discriminated union.
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@ -34,7 +35,8 @@ class MCOperand {
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kRegister, ///< Register operand.
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kImmediate, ///< Immediate operand.
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kFPImmediate, ///< Floating-point immediate operand.
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kExpr ///< Relocatable immediate operand.
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kExpr, ///< Relocatable immediate operand.
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kInst ///< Sub-instruction operand.
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};
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unsigned char Kind;
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@ -43,6 +45,7 @@ class MCOperand {
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int64_t ImmVal;
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double FPImmVal;
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const MCExpr *ExprVal;
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const MCInst *InstVal;
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};
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public:
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@ -53,6 +56,7 @@ public:
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bool isImm() const { return Kind == kImmediate; }
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bool isFPImm() const { return Kind == kFPImmediate; }
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bool isExpr() const { return Kind == kExpr; }
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bool isInst() const { return Kind == kInst; }
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/// getReg - Returns the register number.
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unsigned getReg() const {
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@ -94,6 +98,15 @@ public:
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ExprVal = Val;
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}
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const MCInst *getInst() const {
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assert(isInst() && "This is not a sub-instruction");
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return InstVal;
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}
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void setInst(const MCInst *Val) {
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assert(isInst() && "This is not a sub-instruction");
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InstVal = Val;
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}
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static MCOperand CreateReg(unsigned Reg) {
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MCOperand Op;
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Op.Kind = kRegister;
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@ -118,6 +131,12 @@ public:
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Op.ExprVal = Val;
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return Op;
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}
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static MCOperand CreateInst(const MCInst *Val) {
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MCOperand Op;
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Op.Kind = kInst;
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Op.InstVal = Val;
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return Op;
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}
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void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
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void dump() const;
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