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Fixe typos and 80 column size problems

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2008-07-09 04:45:36 +00:00
parent b4d1bc989e
commit 7b76da145b
9 changed files with 28 additions and 25 deletions
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6
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -148,7 +148,7 @@ emitMaskDirective(MachineFunction &MF)
O << "," << Offset << "\n";
}
/// TODO: Mask Directive for Float Point
/// TODO: Mask Directive for Floating Point
void MipsAsmPrinter::
emitFMaskDirective(MachineFunction &MF)
{
@ -191,14 +191,14 @@ emitSetDirective(SetDirectiveFlags Flag)
}
// Create a bitmask with all callee saved registers for CPU
// or Float Point registers. For CPU registers consider RA,
// or Floating Point registers. For CPU registers consider RA,
// GP and FP for saving if necessary.
unsigned int MipsAsmPrinter::
getSavedRegsBitmask(bool isFloat, MachineFunction &MF)
{
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
// Float Point Registers, TODO
// Floating Point Registers, TODO
if (isFloat)
return 0;

4
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -275,8 +275,8 @@ Select(SDOperand N)
SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
SDOperand InFlag = SDOperand(Node, 0);
SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MVT::Flag, InFlag);
SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32,
MVT::Flag, InFlag);
InFlag = SDOperand(Lo,1);
SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);

2
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -804,7 +804,7 @@ getConstraintType(const std::string &Constraint) const
// unless generating MIPS16 code.
// 'y' : Equivalent to r; retained for
// backwards compatibility.
// 'f' : Float Point registers.
// 'f' : Floating Point registers.
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default : break;

4
lib/Target/Mips/MipsISelLowering.h
View File

@ -40,10 +40,10 @@ namespace llvm {
// Select CC Pseudo Instruction
SelectCC,
// Float Point Branch Conditional
// Floating Point Branch Conditional
FPBrcond,
// Float Point Compare
// Floating Point Compare
FPCmp,
// Return

23
lib/Target/Mips/MipsInstrFPU.td
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@ -12,7 +12,7 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Float Point Instructions
// Floating Point Instructions
// ------------------------
// * 64bit fp:
// - 32 64-bit registers (default mode)
@ -23,7 +23,7 @@
// - 32 32-bit registers (within single-only mode)
//===----------------------------------------------------------------------===//
// Float Point Compare and Branch
// Floating Point Compare and Branch
def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisSameAs<0, 2>, SDTCisInt<0>,
SDTCisVT<1, OtherVT>]>;
def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<0>,
@ -98,7 +98,8 @@ class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs, FGR32:$ft),
def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
(ins FGR32:$fs, FGR32:$ft),
!strconcat(asmstr, ".s $fd, $fs, $ft"),
[(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>,
Requires<[IsSingleFloat]>;
@ -117,7 +118,7 @@ multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
}
//===----------------------------------------------------------------------===//
// Float Point Instructions
// Floating Point Instructions
//===----------------------------------------------------------------------===//
let ft = 0 in {
@ -199,7 +200,7 @@ let fd = 0 in {
"mtc1 $fs, $rt", []>;
}
/// Float Point Memory Instructions
/// Floating Point Memory Instructions
let Predicates = [IsNotSingleFloat] in {
def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
"ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
@ -216,8 +217,8 @@ def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
def LWC1A : FFI<0b110001, (outs AFGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
[(set AFGR32:$ft, (load addr:$addr))]>;
def SWC1A : FFI<0b111001, (outs), (ins AFGR32:$ft, mem:$addr), "swc1 $ft, $addr",
[(store AFGR32:$ft, addr:$addr)]>;
def SWC1A : FFI<0b111001, (outs), (ins AFGR32:$ft, mem:$addr),
"swc1 $ft, $addr", [(store AFGR32:$ft, addr:$addr)]>;
/// Floating-point Aritmetic
defm FADD : FFR1_4<0x10, "add", fadd>;
@ -226,7 +227,7 @@ defm FMUL : FFR1_4<0x02, "mul", fmul>;
defm FSUB : FFR1_4<0x01, "sub", fsub>;
//===----------------------------------------------------------------------===//
// Float Point Branch Codes
// Floating Point Branch Codes
//===----------------------------------------------------------------------===//
// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
// They must be kept in synch.
@ -235,7 +236,7 @@ def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
def MIPS_BRANCH_FL : PatLeaf<(i32 2)>;
def MIPS_BRANCH_TL : PatLeaf<(i32 3)>;
/// Float Point Branch of False/True (Likely)
/// Floating Point Branch of False/True (Likely)
let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in {
class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (ops),
(ins brtarget:$dst), !strconcat(asmstr, " $dst"),
@ -247,7 +248,7 @@ def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
//===----------------------------------------------------------------------===//
// Float Point Flag Conditions
// Floating Point Flag Conditions
//===----------------------------------------------------------------------===//
// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
// They must be kept in synch.
@ -287,7 +288,7 @@ let hasDelaySlot = 1, Defs=[FCR31] in {
}
//===----------------------------------------------------------------------===//
// Float Point Patterns
// Floating Point Patterns
//===----------------------------------------------------------------------===//
def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;

2
lib/Target/Mips/MipsInstrFormats.td
View File

@ -104,7 +104,7 @@ class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
//===----------------------------------------------------------------------===//
//
// FLOAT POINT INSTRUCTION FORMATS
// FLOATING POINT INSTRUCTION FORMATS
//
// opcode - operation code.
// fs - src reg.

3
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -289,7 +289,8 @@ foldMemoryOperand(MachineFunction &MF,
case Mips::FMOV_D32:
if ((MI->getOperand(0).isRegister()) &&
(MI->getOperand(1).isRegister())) {
const TargetRegisterClass *RC = RI.getRegClass(MI->getOperand(0).getReg());
const TargetRegisterClass
*RC = RI.getRegClass(MI->getOperand(0).getReg());
unsigned StoreOpc, LoadOpc;
if (RC == Mips::FGR32RegisterClass) {

3
lib/Target/Mips/MipsInstrInfo.h
View File

@ -160,7 +160,8 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
virtual void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;

6
lib/Target/Mips/MipsSubtarget.h
View File

@ -45,16 +45,16 @@ protected:
// IsSingleFloat - The target only supports single precision float
// point operations. This enable the target to use all 32 32-bit
// float point registers instead of only using even ones.
// floating point registers instead of only using even ones.
bool IsSingleFloat;
// IsFP64bit - The target processor has 64-bit float point registers.
// IsFP64bit - The target processor has 64-bit floating point registers.
bool IsFP64bit;
// IsFP64bit - General-purpose registers are 64 bits wide
bool IsGP64bit;
// HasAllegrexVFPU - Allegrex processor has a vector float point unit.
// HasAllegrexVFPU - Allegrex processor has a vector floating point unit.
bool HasAllegrexVFPU;
// IsAllegrex - The target processor is a Allegrex core.