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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-04 10:30:01 +00:00
Move the list of register classes into CodeGenRegBank as well.
No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -237,6 +237,14 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
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// Assign the enumeration values.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i)
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Registers.push_back(CodeGenRegister(Regs[i], i + 1));
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// Read in register class definitions.
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std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
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if (RCs.empty())
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throw std::string("No 'RegisterClass' subclasses defined!");
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RegClasses.reserve(RCs.size());
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RegClasses.assign(RCs.begin(), RCs.end());
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}
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CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
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@ -250,6 +258,17 @@ CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
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throw TGError(Def->getLoc(), "Not a known Register!");
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}
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CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
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if (Def2RC.empty())
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for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
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Def2RC[RegClasses[i].TheDef] = &RegClasses[i];
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if (CodeGenRegisterClass *RC = Def2RC[Def])
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return RC;
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throw TGError(Def->getLoc(), "Not a known RegisterClass!");
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}
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Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
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bool create) {
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// Look for an existing entry.
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@ -406,3 +425,55 @@ void CodeGenRegBank::computeDerivedInfo() {
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computeComposites();
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}
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/// getRegisterClassForRegister - Find the register class that contains the
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/// specified physical register. If the register is not in a register class,
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/// return null. If the register is in multiple classes, and the classes have a
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/// superset-subset relationship and the same set of types, return the
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/// superclass. Otherwise return null.
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const CodeGenRegisterClass*
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CodeGenRegBank::getRegClassForRegister(Record *R) {
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const std::vector<CodeGenRegisterClass> &RCs = getRegClasses();
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const CodeGenRegisterClass *FoundRC = 0;
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RCs[i];
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if (!RC.containsRegister(R))
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continue;
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// If this is the first class that contains the register,
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// make a note of it and go on to the next class.
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if (!FoundRC) {
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FoundRC = &RC;
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continue;
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}
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// If a register's classes have different types, return null.
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if (RC.getValueTypes() != FoundRC->getValueTypes())
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return 0;
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std::vector<Record *> Elements(RC.Elements);
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std::vector<Record *> FoundElements(FoundRC->Elements);
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std::sort(Elements.begin(), Elements.end());
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std::sort(FoundElements.begin(), FoundElements.end());
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// Check to see if the previously found class that contains
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// the register is a subclass of the current class. If so,
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// prefer the superclass.
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if (std::includes(Elements.begin(), Elements.end(),
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FoundElements.begin(), FoundElements.end())) {
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FoundRC = &RC;
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continue;
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}
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// Check to see if the previously found class that contains
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// the register is a superclass of the current class. If so,
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// prefer the superclass.
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if (std::includes(FoundElements.begin(), FoundElements.end(),
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Elements.begin(), Elements.end()))
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continue;
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// Multiple classes, and neither is a superclass of the other.
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// Return null.
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return 0;
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}
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return FoundRC;
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}
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@ -153,6 +153,9 @@ namespace llvm {
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std::vector<CodeGenRegister> Registers;
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DenseMap<Record*, CodeGenRegister*> Def2Reg;
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std::vector<CodeGenRegisterClass> RegClasses;
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DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
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// Composite SubRegIndex instances.
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// Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
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typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
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@ -181,6 +184,20 @@ namespace llvm {
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// Find a register from its Record def.
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CodeGenRegister *getReg(Record*);
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const std::vector<CodeGenRegisterClass> &getRegClasses() {
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return RegClasses;
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}
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// Find a register class from its def.
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CodeGenRegisterClass *getRegClass(Record*);
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/// getRegisterClassForRegister - Find the register class that contains the
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/// specified physical register. If the register is not in a register
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/// class, return null. If the register is in multiple classes, and the
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/// classes have a superset-subset relationship and the same set of types,
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/// return the superclass. Otherwise return null.
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const CodeGenRegisterClass* getRegClassForRegister(Record *R);
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// Computed derived records such as missing sub-register indices.
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void computeDerivedInfo();
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@ -163,16 +163,6 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
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return *RegBank;
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}
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void CodeGenTarget::ReadRegisterClasses() const {
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std::vector<Record*> RegClasses =
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Records.getAllDerivedDefinitions("RegisterClass");
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if (RegClasses.empty())
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throw std::string("No 'RegisterClass' subclasses defined!");
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RegisterClasses.reserve(RegClasses.size());
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RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
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}
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/// getRegisterByName - If there is a register with the specific AsmName,
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/// return it.
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const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
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@ -191,7 +181,7 @@ getRegisterVTs(Record *R) const {
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std::vector<MVT::SimpleValueType> Result;
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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const CodeGenRegisterClass &RC = RCs[i];
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for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
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if (R == RC.Elements[ei]) {
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const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
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@ -66,9 +66,7 @@ class CodeGenTarget {
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mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
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mutable CodeGenRegBank *RegBank;
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mutable std::vector<CodeGenRegisterClass> RegisterClasses;
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mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
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void ReadRegisterClasses() const;
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void ReadInstructions() const;
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void ReadLegalValueTypes() const;
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@ -107,71 +105,11 @@ public:
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const CodeGenRegister *getRegisterByName(StringRef Name) const;
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const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
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if (RegisterClasses.empty()) ReadRegisterClasses();
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return RegisterClasses;
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return getRegBank().getRegClasses();
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}
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const CodeGenRegisterClass &getRegisterClass(Record *R) const {
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const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
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for (unsigned i = 0, e = RC.size(); i != e; ++i)
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if (RC[i].TheDef == R)
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return RC[i];
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assert(0 && "Didn't find the register class");
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abort();
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}
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/// getRegisterClassForRegister - Find the register class that contains the
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/// specified physical register. If the register is not in a register
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/// class, return null. If the register is in multiple classes, and the
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/// classes have a superset-subset relationship and the same set of
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/// types, return the superclass. Otherwise return null.
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const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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const CodeGenRegisterClass *FoundRC = 0;
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
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if (R != RC.Elements[ei])
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continue;
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// If a register's classes have different types, return null.
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if (FoundRC && RC.getValueTypes() != FoundRC->getValueTypes())
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return 0;
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// If this is the first class that contains the register,
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// make a note of it and go on to the next class.
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if (!FoundRC) {
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FoundRC = &RC;
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break;
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}
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std::vector<Record *> Elements(RC.Elements);
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std::vector<Record *> FoundElements(FoundRC->Elements);
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std::sort(Elements.begin(), Elements.end());
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std::sort(FoundElements.begin(), FoundElements.end());
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// Check to see if the previously found class that contains
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// the register is a subclass of the current class. If so,
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// prefer the superclass.
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if (std::includes(Elements.begin(), Elements.end(),
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FoundElements.begin(), FoundElements.end())) {
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FoundRC = &RC;
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break;
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}
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// Check to see if the previously found class that contains
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// the register is a superclass of the current class. If so,
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// prefer the superclass.
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if (std::includes(FoundElements.begin(), FoundElements.end(),
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Elements.begin(), Elements.end()))
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break;
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// Multiple classes, and neither is a superclass of the other.
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// Return null.
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return 0;
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}
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}
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return FoundRC;
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return *getRegBank().getRegClass(R);
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}
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/// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
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@ -250,7 +250,7 @@ struct OperandsSignature {
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if (OpLeafRec->isSubClassOf("RegisterClass"))
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RC = &Target.getRegisterClass(OpLeafRec);
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else if (OpLeafRec->isSubClassOf("Register"))
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RC = Target.getRegisterClassForRegister(OpLeafRec);
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RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
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else
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return false;
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