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Check whether MCInst operand isImm before calling getImm.

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When processing possible aliases, TableGen assumes that if an operand *can* be
an immediate, then it always *will* be. This is incorrect for the AArch64
backend. This patch inserts a check in the generated code to make sure isImm is
true first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-01-09 13:32:04 +00:00
parent 2c8cf4b404
commit 7bf2e1b9ef
1 changed files with 10 additions and 4 deletions
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14
utils/TableGen/AsmWriterEmitter.cpp
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@ -863,12 +863,18 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
break;
}
case CodeGenInstAlias::ResultOperand::K_Imm:
Cond = std::string("MI->getOperand(") +
llvm::utostr(i) + ").getImm() == " +
llvm::utostr(CGA->ResultOperands[i].getImm());
case CodeGenInstAlias::ResultOperand::K_Imm: {
std::string Op = "MI->getOperand(" + llvm::utostr(i) + ")";
// Just because the alias has an immediate result, doesn't mean the
// MCInst will. An MCExpr could be present, for example.
IAP->addCond(Op + ".isImm()");
Cond = Op + ".getImm() == "
+ llvm::utostr(CGA->ResultOperands[i].getImm());
IAP->addCond(Cond);
break;
}
case CodeGenInstAlias::ResultOperand::K_Reg:
// If this is zero_reg, something's playing tricks we're not
// equipped to handle.