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Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:

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we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24859 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-12-19 07:57:53 +00:00
parent 1b80f4d2c6
commit 7c423b4df1
2 changed files with 8 additions and 2 deletions
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5
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@@ -456,6 +456,8 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
if (RegValuesToPass.size() >= 6) { if (RegValuesToPass.size() >= 6) {
ValToStore = Lo; ValToStore = Lo;
ArgOffset += 4;
ObjSize = 4;
} else { } else {
RegValuesToPass.push_back(Lo); RegValuesToPass.push_back(Lo);
} }
@@ -464,7 +466,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
if (ValToStore.Val) { if (ValToStore.Val) {
if (!StackPtr.Val) { if (!StackPtr.Val) {
StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32); StackPtr = DAG.getRegister(V8::O6, MVT::i32);
NullSV = DAG.getSrcValue(NULL); NullSV = DAG.getSrcValue(NULL);
} }
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
@@ -893,6 +895,7 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: break; default: break;
case ISD::Register: return Op;
case ISD::FrameIndex: { case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex(); int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse()) if (N->hasOneUse())

5
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@@ -456,6 +456,8 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
if (RegValuesToPass.size() >= 6) { if (RegValuesToPass.size() >= 6) {
ValToStore = Lo; ValToStore = Lo;
ArgOffset += 4;
ObjSize = 4;
} else { } else {
RegValuesToPass.push_back(Lo); RegValuesToPass.push_back(Lo);
} }
@@ -464,7 +466,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
if (ValToStore.Val) { if (ValToStore.Val) {
if (!StackPtr.Val) { if (!StackPtr.Val) {
StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32); StackPtr = DAG.getRegister(V8::O6, MVT::i32);
NullSV = DAG.getSrcValue(NULL); NullSV = DAG.getSrcValue(NULL);
} }
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
@@ -893,6 +895,7 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: break; default: break;
case ISD::Register: return Op;
case ISD::FrameIndex: { case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex(); int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse()) if (N->hasOneUse())