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Change the PassManager from a reference to a pointer.

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The TargetPassManager's default constructor wants to initialize the PassManager
to 'null'. But it's illegal to bind a null reference to a null l-value. Make the
ivar a pointer instead.
PR12468


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2012-05-01 08:27:43 +00:00
parent c80e7d2ea4
commit 7c4ce30ea6
13 changed files with 69 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/Passes.h
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@ -56,7 +56,7 @@ public:
protected: protected:
TargetMachine *TM; TargetMachine *TM;
PassManagerBase ± PassManagerBase *PM;
PassConfigImpl *Impl; // Internal data structures PassConfigImpl *Impl; // Internal data structures
bool Initialized; // Flagged after all passes are configured. bool Initialized; // Flagged after all passes are configured.

42
lib/CodeGen/Passes.cpp
View File

@ -207,7 +207,7 @@ TargetPassConfig::~TargetPassConfig() {
// Out of line constructor provides default values for pass options and // Out of line constructor provides default values for pass options and
// registers all common codegen passes. // registers all common codegen passes.
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
: ImmutablePass(ID), TM(tm), PM(pm), Impl(0), Initialized(false), : ImmutablePass(ID), TM(tm), PM(&pm), Impl(0), Initialized(false),
DisableVerify(false), DisableVerify(false),
EnableTailMerge(true) { EnableTailMerge(true) {
@ -234,7 +234,7 @@ TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
} }
TargetPassConfig::TargetPassConfig() TargetPassConfig::TargetPassConfig()
: ImmutablePass(ID), PM(*(PassManagerBase*)0) { : ImmutablePass(ID), PM(0) {
llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
} }
@ -269,16 +269,16 @@ AnalysisID TargetPassConfig::addPass(char &ID) {
Pass *P = Pass::createPass(FinalID); Pass *P = Pass::createPass(FinalID);
if (!P) if (!P)
llvm_unreachable("Pass ID not registered"); llvm_unreachable("Pass ID not registered");
PM.add(P); PM->add(P);
return FinalID; return FinalID;
} }
void TargetPassConfig::printAndVerify(const char *Banner) const { void TargetPassConfig::printAndVerify(const char *Banner) const {
if (TM->shouldPrintMachineCode()) if (TM->shouldPrintMachineCode())
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
if (VerifyMachineCode) if (VerifyMachineCode)
PM.add(createMachineVerifierPass(Banner)); PM->add(createMachineVerifierPass(Banner));
} }
/// Add common target configurable passes that perform LLVM IR to IR transforms /// Add common target configurable passes that perform LLVM IR to IR transforms
@ -288,46 +288,46 @@ void TargetPassConfig::addIRPasses() {
// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
// BasicAliasAnalysis wins if they disagree. This is intended to help // BasicAliasAnalysis wins if they disagree. This is intended to help
// support "obvious" type-punning idioms. // support "obvious" type-punning idioms.
PM.add(createTypeBasedAliasAnalysisPass()); PM->add(createTypeBasedAliasAnalysisPass());
PM.add(createBasicAliasAnalysisPass()); PM->add(createBasicAliasAnalysisPass());
// Before running any passes, run the verifier to determine if the input // Before running any passes, run the verifier to determine if the input
// coming from the front-end and/or optimizer is valid. // coming from the front-end and/or optimizer is valid.
if (!DisableVerify) if (!DisableVerify)
PM.add(createVerifierPass()); PM->add(createVerifierPass());
// Run loop strength reduction before anything else. // Run loop strength reduction before anything else.
if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering())); PM->add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR) if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); PM->add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
} }
PM.add(createGCLoweringPass()); PM->add(createGCLoweringPass());
// Make sure that no unreachable blocks are instruction selected. // Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass()); PM->add(createUnreachableBlockEliminationPass());
} }
/// Add common passes that perform LLVM IR to IR transforms in preparation for /// Add common passes that perform LLVM IR to IR transforms in preparation for
/// instruction selection. /// instruction selection.
void TargetPassConfig::addISelPrepare() { void TargetPassConfig::addISelPrepare() {
if (getOptLevel() != CodeGenOpt::None && !DisableCGP) if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering())); PM->add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering())); PM->add(createStackProtectorPass(getTargetLowering()));
addPreISel(); addPreISel();
if (PrintISelInput) if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n" PM->add(createPrintFunctionPass("\n\n"
"*** Final LLVM Code input to ISel ***\n", "*** Final LLVM Code input to ISel ***\n",
&dbgs())); &dbgs()));
// All passes which modify the LLVM IR are now complete; run the verifier // All passes which modify the LLVM IR are now complete; run the verifier
// to ensure that the IR is valid. // to ensure that the IR is valid.
if (!DisableVerify) if (!DisableVerify)
PM.add(createVerifierPass()); PM->add(createVerifierPass());
} }
/// Add the complete set of target-independent postISel code generator passes. /// Add the complete set of target-independent postISel code generator passes.
@ -405,7 +405,7 @@ void TargetPassConfig::addMachinePasses() {
// GC // GC
addPass(GCMachineCodeAnalysisID); addPass(GCMachineCodeAnalysisID);
if (PrintGCInfo) if (PrintGCInfo)
PM.add(createGCInfoPrinter(dbgs())); PM->add(createGCInfoPrinter(dbgs()));
// Basic block placement. // Basic block placement.
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
@ -522,7 +522,7 @@ void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
addPass(PHIEliminationID); addPass(PHIEliminationID);
addPass(TwoAddressInstructionPassID); addPass(TwoAddressInstructionPassID);
PM.add(RegAllocPass); PM->add(RegAllocPass);
printAndVerify("After Register Allocation"); printAndVerify("After Register Allocation");
} }
@ -564,7 +564,7 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
printAndVerify("After Machine Scheduling"); printAndVerify("After Machine Scheduling");
// Add the selected register allocation pass. // Add the selected register allocation pass.
PM.add(RegAllocPass); PM->add(RegAllocPass);
printAndVerify("After Register Allocation"); printAndVerify("After Register Allocation");
// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature, // FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,

20
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -136,22 +136,22 @@ TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
bool ARMPassConfig::addPreISel() { bool ARMPassConfig::addPreISel() {
if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge) if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
PM.add(createGlobalMergePass(TM->getTargetLowering())); PM->add(createGlobalMergePass(TM->getTargetLowering()));
return false; return false;
} }
bool ARMPassConfig::addInstSelector() { bool ARMPassConfig::addInstSelector() {
PM.add(createARMISelDag(getARMTargetMachine(), getOptLevel())); PM->add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
return false; return false;
} }
bool ARMPassConfig::addPreRegAlloc() { bool ARMPassConfig::addPreRegAlloc() {
// FIXME: temporarily disabling load / store optimization pass for Thumb1. // FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only()) if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass(true)); PM->add(createARMLoadStoreOptimizationPass(true));
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9()) if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
PM.add(createMLxExpansionPass()); PM->add(createMLxExpansionPass());
return true; return true;
} }
@ -159,23 +159,23 @@ bool ARMPassConfig::addPreSched2() {
// FIXME: temporarily disabling load / store optimization pass for Thumb1. // FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only()) { if (!getARMSubtarget().isThumb1Only()) {
PM.add(createARMLoadStoreOptimizationPass()); PM->add(createARMLoadStoreOptimizationPass());
printAndVerify("After ARM load / store optimizer"); printAndVerify("After ARM load / store optimizer");
} }
if (getARMSubtarget().hasNEON()) if (getARMSubtarget().hasNEON())
PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass)); PM->add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
} }
// Expand some pseudo instructions into multiple instructions to allow // Expand some pseudo instructions into multiple instructions to allow
// proper scheduling. // proper scheduling.
PM.add(createARMExpandPseudoPass()); PM->add(createARMExpandPseudoPass());
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only()) if (!getARMSubtarget().isThumb1Only())
addPass(IfConverterID); addPass(IfConverterID);
} }
if (getARMSubtarget().isThumb2()) if (getARMSubtarget().isThumb2())
PM.add(createThumb2ITBlockPass()); PM->add(createThumb2ITBlockPass());
return true; return true;
} }
@ -183,13 +183,13 @@ bool ARMPassConfig::addPreSched2() {
bool ARMPassConfig::addPreEmitPass() { bool ARMPassConfig::addPreEmitPass() {
if (getARMSubtarget().isThumb2()) { if (getARMSubtarget().isThumb2()) {
if (!getARMSubtarget().prefers32BitThumb()) if (!getARMSubtarget().prefers32BitThumb())
PM.add(createThumb2SizeReductionPass()); PM->add(createThumb2SizeReductionPass());
// Constant island pass work on unbundled instructions. // Constant island pass work on unbundled instructions.
addPass(UnpackMachineBundlesID); addPass(UnpackMachineBundlesID);
} }
PM.add(createARMConstantIslandPass()); PM->add(createARMConstantIslandPass());
return true; return true;
} }

6
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -72,7 +72,7 @@ TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) {
bool SPUPassConfig::addInstSelector() { bool SPUPassConfig::addInstSelector() {
// Install an instruction selector. // Install an instruction selector.
PM.add(createSPUISelDag(getSPUTargetMachine())); PM->add(createSPUISelDag(getSPUTargetMachine()));
return false; return false;
} }
@ -85,9 +85,9 @@ bool SPUPassConfig::addPreEmitPass() {
(BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol( (BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
"createTCESchedulerPass"); "createTCESchedulerPass");
if (schedulerCreator != NULL) if (schedulerCreator != NULL)
PM.add(schedulerCreator("cellspu")); PM->add(schedulerCreator("cellspu"));
//align instructions with nops/lnops for dual issue //align instructions with nops/lnops for dual issue
PM.add(createSPUNopFillerPass(getSPUTargetMachine())); PM->add(createSPUNopFillerPass(getSPUTargetMachine()));
return true; return true;
} }

16
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -100,23 +100,23 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
} }
bool HexagonPassConfig::addInstSelector() { bool HexagonPassConfig::addInstSelector() {
PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine())); PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
PM.add(createHexagonISelDag(getHexagonTargetMachine())); PM->add(createHexagonISelDag(getHexagonTargetMachine()));
PM.add(createHexagonPeephole()); PM->add(createHexagonPeephole());
return false; return false;
} }
bool HexagonPassConfig::addPreRegAlloc() { bool HexagonPassConfig::addPreRegAlloc() {
if (!DisableHardwareLoops) { if (!DisableHardwareLoops) {
PM.add(createHexagonHardwareLoops()); PM->add(createHexagonHardwareLoops());
} }
return false; return false;
} }
bool HexagonPassConfig::addPostRegAlloc() { bool HexagonPassConfig::addPostRegAlloc() {
PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine())); PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
return true; return true;
} }
@ -129,14 +129,14 @@ bool HexagonPassConfig::addPreSched2() {
bool HexagonPassConfig::addPreEmitPass() { bool HexagonPassConfig::addPreEmitPass() {
if (!DisableHardwareLoops) { if (!DisableHardwareLoops) {
PM.add(createHexagonFixupHwLoops()); PM->add(createHexagonFixupHwLoops());
} }
// Expand Spill code for predicate registers. // Expand Spill code for predicate registers.
PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine())); PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
// Split up TFRcondsets into conditional transfers. // Split up TFRcondsets into conditional transfers.
PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine())); PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
return false; return false;
} }

4
lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -68,7 +68,7 @@ TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM) {
// Install an instruction selector pass using // Install an instruction selector pass using
// the ISelDag to gen MBlaze code. // the ISelDag to gen MBlaze code.
bool MBlazePassConfig::addInstSelector() { bool MBlazePassConfig::addInstSelector() {
PM.add(createMBlazeISelDag(getMBlazeTargetMachine())); PM->add(createMBlazeISelDag(getMBlazeTargetMachine()));
return false; return false;
} }
@ -76,6 +76,6 @@ bool MBlazePassConfig::addInstSelector() {
// machine code is emitted. return true if -print-machineinstrs should // machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes. // print out the code after the passes.
bool MBlazePassConfig::addPreEmitPass() { bool MBlazePassConfig::addPreEmitPass() {
PM.add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine())); PM->add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
return true; return true;
} }

4
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -60,12 +60,12 @@ TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
bool MSP430PassConfig::addInstSelector() { bool MSP430PassConfig::addInstSelector() {
// Install an instruction selector. // Install an instruction selector.
PM.add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel())); PM->add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
return false; return false;
} }
bool MSP430PassConfig::addPreEmitPass() { bool MSP430PassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer. // Must run branch selection immediately preceding the asm printer.
PM.add(createMSP430BranchSelectionPass()); PM->add(createMSP430BranchSelectionPass());
return false; return false;
} }

14
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -117,18 +117,16 @@ TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
// Install an instruction selector pass using // Install an instruction selector pass using
// the ISelDag to gen Mips code. // the ISelDag to gen Mips code.
bool MipsPassConfig::addInstSelector() bool MipsPassConfig::addInstSelector() {
{ PM->add(createMipsISelDag(getMipsTargetMachine()));
PM.add(createMipsISelDag(getMipsTargetMachine()));
return false; return false;
} }
// Implemented by targets that want to run passes immediately before // Implemented by targets that want to run passes immediately before
// machine code is emitted. return true if -print-machineinstrs should // machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes. // print out the code after the passes.
bool MipsPassConfig::addPreEmitPass() bool MipsPassConfig::addPreEmitPass() {
{ PM->add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
PM.add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
return true; return true;
} }
@ -136,12 +134,12 @@ bool MipsPassConfig::addPreRegAlloc() {
// Do not restore $gp if target is Mips64. // Do not restore $gp if target is Mips64.
// In N32/64, $gp is a callee-saved register. // In N32/64, $gp is a callee-saved register.
if (!getMipsSubtarget().hasMips64()) if (!getMipsSubtarget().hasMips64())
PM.add(createMipsEmitGPRestorePass(getMipsTargetMachine())); PM->add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
return true; return true;
} }
bool MipsPassConfig::addPreSched2() { bool MipsPassConfig::addPreSched2() {
PM.add(createMipsExpandPseudoPass(getMipsTargetMachine())); PM->add(createMipsExpandPseudoPass(getMipsTargetMachine()));
return true; return true;
} }

8
lib/Target/PTX/PTXTargetMachine.cpp
View File

@ -130,7 +130,7 @@ TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM) {
} }
bool PTXPassConfig::addInstSelector() { bool PTXPassConfig::addInstSelector() {
PM.add(createPTXISelDag(getPTXTargetMachine(), getOptLevel())); PM->add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
return false; return false;
} }
@ -145,7 +145,7 @@ void PTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
bool PTXPassConfig::addPostRegAlloc() { bool PTXPassConfig::addPostRegAlloc() {
// PTXMFInfoExtract must after register allocation! // PTXMFInfoExtract must after register allocation!
//PM.add(createPTXMFInfoExtract(getPTXTargetMachine())); //PM->add(createPTXMFInfoExtract(getPTXTargetMachine()));
return false; return false;
} }
@ -159,7 +159,7 @@ void PTXPassConfig::addMachineLateOptimization() {
} }
bool PTXPassConfig::addPreEmitPass() { bool PTXPassConfig::addPreEmitPass() {
PM.add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel())); PM->add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
PM.add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel())); PM->add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
return true; return true;
} }

4
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -98,13 +98,13 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
bool PPCPassConfig::addInstSelector() { bool PPCPassConfig::addInstSelector() {
// Install an instruction selector. // Install an instruction selector.
PM.add(createPPCISelDag(getPPCTargetMachine())); PM->add(createPPCISelDag(getPPCTargetMachine()));
return false; return false;
} }
bool PPCPassConfig::addPreEmitPass() { bool PPCPassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer. // Must run branch selection immediately preceding the asm printer.
PM.add(createPPCBranchSelectionPass()); PM->add(createPPCBranchSelectionPass());
return false; return false;
} }

6
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -59,7 +59,7 @@ TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
} }
bool SparcPassConfig::addInstSelector() { bool SparcPassConfig::addInstSelector() {
PM.add(createSparcISelDag(getSparcTargetMachine())); PM->add(createSparcISelDag(getSparcTargetMachine()));
return false; return false;
} }
@ -67,8 +67,8 @@ bool SparcPassConfig::addInstSelector() {
/// passes immediately before machine code is emitted. This should return /// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes. /// true if -print-machineinstrs should print out the code after the passes.
bool SparcPassConfig::addPreEmitPass(){ bool SparcPassConfig::addPreEmitPass(){
PM.add(createSparcFPMoverPass(getSparcTargetMachine())); PM->add(createSparcFPMoverPass(getSparcTargetMachine()));
PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine())); PM->add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
return true; return true;
} }

12
lib/Target/X86/X86TargetMachine.cpp
View File

@ -145,34 +145,34 @@ TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
bool X86PassConfig::addInstSelector() { bool X86PassConfig::addInstSelector() {
// Install an instruction selector. // Install an instruction selector.
PM.add(createX86ISelDag(getX86TargetMachine(), getOptLevel())); PM->add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
// For 32-bit, prepend instructions to set the "global base reg" for PIC. // For 32-bit, prepend instructions to set the "global base reg" for PIC.
if (!getX86Subtarget().is64Bit()) if (!getX86Subtarget().is64Bit())
PM.add(createGlobalBaseRegPass()); PM->add(createGlobalBaseRegPass());
return false; return false;
} }
bool X86PassConfig::addPreRegAlloc() { bool X86PassConfig::addPreRegAlloc() {
PM.add(createX86MaxStackAlignmentHeuristicPass()); PM->add(createX86MaxStackAlignmentHeuristicPass());
return false; // -print-machineinstr shouldn't print after this. return false; // -print-machineinstr shouldn't print after this.
} }
bool X86PassConfig::addPostRegAlloc() { bool X86PassConfig::addPostRegAlloc() {
PM.add(createX86FloatingPointStackifierPass()); PM->add(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this. return true; // -print-machineinstr should print after this.
} }
bool X86PassConfig::addPreEmitPass() { bool X86PassConfig::addPreEmitPass() {
bool ShouldPrint = false; bool ShouldPrint = false;
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass)); PM->add(createExecutionDependencyFixPass(&X86::VR128RegClass));
ShouldPrint = true; ShouldPrint = true;
} }
if (getX86Subtarget().hasAVX() && UseVZeroUpper) { if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
PM.add(createX86IssueVZeroUpperPass()); PM->add(createX86IssueVZeroUpperPass());
ShouldPrint = true; ShouldPrint = true;
} }

2
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -55,7 +55,7 @@ TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
} }
bool XCorePassConfig::addInstSelector() { bool XCorePassConfig::addInstSelector() {
PM.add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel())); PM->add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
return false; return false;
} }