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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-09-25 17:20:48 +00:00
Emit TargetRegisterInfo::composeSubRegIndices().
Also verify that all subregister indices compose unambiguously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105064 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -82,6 +82,7 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
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<< " { return false; }\n"
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<< " { return false; }\n"
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<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
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<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
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<< " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
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<< " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
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<< " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
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<< "};\n\n";
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<< "};\n\n";
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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@@ -171,14 +172,28 @@ static void addSubSuperReg(Record *R, Record *S,
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addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
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addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
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}
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}
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// Map SubRegIndex -> Register
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struct RegisterMaps {
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typedef std::map<Record*, Record*, LessRecord> SubRegMap;
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// Map SubRegIndex -> Register
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// Map Register -> SubRegMap
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typedef std::map<Record*, Record*, LessRecord> SubRegMap;
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typedef std::map<Record*, SubRegMap> AllSubRegMap;
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// Map Register -> SubRegMap
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typedef std::map<Record*, SubRegMap> SubRegMaps;
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SubRegMaps SubReg;
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SubRegMap &inferSubRegIndices(Record *Reg);
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// Composite SubRegIndex instances.
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// Map (SubRegIndex,SubRegIndex) -> SubRegIndex
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typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
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CompositeMap Composite;
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// Compute SubRegIndex compositions after inferSubRegIndices has run on all
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// registers.
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void computeComposites();
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};
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// Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
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// Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
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static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) {
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RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) {
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SubRegMap &SRM = ASRM[Reg];
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SubRegMap &SRM = SubReg[Reg];
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if (!SRM.empty())
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if (!SRM.empty())
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return SRM;
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return SRM;
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std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
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std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
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@@ -191,7 +206,7 @@ static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) {
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if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
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if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
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throw "SubRegIndex " + Indices[i]->getName()
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throw "SubRegIndex " + Indices[i]->getName()
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+ " appears twice in Register " + Reg->getName();
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+ " appears twice in Register " + Reg->getName();
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inferSubRegIndices(SubRegs[i], ASRM);
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inferSubRegIndices(SubRegs[i]);
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}
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}
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// Keep track of inherited subregs and how they can be reached.
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// Keep track of inherited subregs and how they can be reached.
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@@ -202,7 +217,7 @@ static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) {
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// Clone inherited subregs. Here the order is important - earlier subregs take
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// Clone inherited subregs. Here the order is important - earlier subregs take
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// precedence.
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// precedence.
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for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
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for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
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SubRegMap &M = ASRM[SubRegs[i]];
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SubRegMap &M = SubReg[SubRegs[i]];
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for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
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for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
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if (!SRM.insert(*si).second)
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if (!SRM.insert(*si).second)
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Orphans[si->second] = std::make_pair(Indices[i], si->first);
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Orphans[si->second] = std::make_pair(Indices[i], si->first);
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@@ -226,8 +241,8 @@ static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) {
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DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
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DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
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if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
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if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw "Invalid SubClassIndex in " + Pat->getAsString();
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throw "Invalid SubClassIndex in " + Pat->getAsString();
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SubRegMap::const_iterator ni = ASRM[R2].find(IdxInit->getDef());
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SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
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if (ni == ASRM[R2].end())
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if (ni == SubReg[R2].end())
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throw "Composite " + Pat->getAsString() + " refers to bad index in "
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throw "Composite " + Pat->getAsString() + " refers to bad index in "
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+ R2->getName();
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+ R2->getName();
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R2 = ni->second;
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R2 = ni->second;
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@@ -255,6 +270,62 @@ static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) {
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return SRM;
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return SRM;
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}
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}
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void RegisterMaps::computeComposites() {
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for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
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sri != sre; ++sri) {
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Record *Reg1 = sri->first;
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const SubRegMap &SRM1 = sri->second;
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for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
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i1 != e1; ++i1) {
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Record *Idx1 = i1->first;
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Record *Reg2 = i1->second;
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// Ignore identity compositions.
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if (Reg1 == Reg2)
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continue;
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// If Reg2 has no subregs, Idx1 doesn't compose.
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if (!SubReg.count(Reg2))
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continue;
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const SubRegMap &SRM2 = SubReg[Reg2];
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// Try composing Idx1 with another SubRegIndex.
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for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
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i2 != e2; ++i2) {
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std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
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Record *Reg3 = i2->second;
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// OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
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for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
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i1d != e1d; ++i1d) {
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// Ignore identity compositions.
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if (Reg2 == Reg3)
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continue;
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if (i1d->second == Reg3) {
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std::pair<CompositeMap::iterator,bool> Ins =
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Composite.insert(std::make_pair(IdxPair, i1d->first));
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// Conflicting composition?
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if (!Ins.second && Ins.first->second != i1d->first) {
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errs() << "Error: SubRegIndex " << getQualifiedName(Idx1)
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<< " and " << getQualifiedName(IdxPair.second)
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<< " compose ambiguously as "
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<< getQualifiedName(Ins.first->second) << " or "
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<< getQualifiedName(i1d->first) << "\n";
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abort();
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}
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}
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}
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}
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}
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}
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// We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
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// compositions, so remove any mappings of that form.
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for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
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i != e;) {
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CompositeMap::iterator j = i;
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++i;
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if (j->first.second == j->second)
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Composite.erase(j);
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}
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}
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class RegisterSorter {
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class RegisterSorter {
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private:
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private:
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std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
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std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
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@@ -836,7 +907,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
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std::string ClassName = Target.getName() + "GenRegisterInfo";
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std::string ClassName = Target.getName() + "GenRegisterInfo";
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// Calculate the mapping of subregister+index pairs to physical registers.
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// Calculate the mapping of subregister+index pairs to physical registers.
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AllSubRegMap AllSRM;
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RegisterMaps RegMaps;
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// Emit the subregister + index mapping function based on the information
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// Emit the subregister + index mapping function based on the information
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// calculated above.
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// calculated above.
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@@ -845,14 +916,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
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<< " switch (RegNo) {\n"
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<< " switch (RegNo) {\n"
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<< " default:\n return 0;\n";
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<< " default:\n return 0;\n";
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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SubRegMap &SRM = inferSubRegIndices(Regs[i].TheDef, AllSRM);
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RegisterMaps::SubRegMap &SRM = RegMaps.inferSubRegIndices(Regs[i].TheDef);
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if (SRM.empty())
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if (SRM.empty())
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continue;
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continue;
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OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
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OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
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OS << " switch (Index) {\n";
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OS << " switch (Index) {\n";
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OS << " default: return 0;\n";
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OS << " default: return 0;\n";
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for (SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie;
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for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
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++ii)
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ie = SRM.end(); ii != ie; ++ii)
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OS << " case " << getQualifiedName(ii->first)
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OS << " case " << getQualifiedName(ii->first)
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<< ": return " << getQualifiedName(ii->second) << ";\n";
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<< ": return " << getQualifiedName(ii->second) << ";\n";
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OS << " };\n" << " break;\n";
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OS << " };\n" << " break;\n";
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@@ -866,12 +937,12 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
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<< " switch (RegNo) {\n"
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<< " switch (RegNo) {\n"
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<< " default:\n return 0;\n";
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<< " default:\n return 0;\n";
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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SubRegMap &SRM = AllSRM[Regs[i].TheDef];
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RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
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if (SRM.empty())
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if (SRM.empty())
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continue;
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continue;
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OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
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OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
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for (SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie;
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for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
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++ii)
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ie = SRM.end(); ii != ie; ++ii)
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OS << " if (SubRegNo == " << getQualifiedName(ii->second)
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OS << " if (SubRegNo == " << getQualifiedName(ii->second)
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<< ") return " << getQualifiedName(ii->first) << ";\n";
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<< ") return " << getQualifiedName(ii->first) << ";\n";
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OS << " return 0;\n";
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OS << " return 0;\n";
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@@ -879,7 +950,32 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
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OS << " };\n";
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OS << " };\n";
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OS << " return 0;\n";
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OS << " return 0;\n";
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OS << "}\n\n";
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OS << "}\n\n";
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// Emit composeSubRegIndices
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RegMaps.computeComposites();
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OS << "unsigned " << ClassName
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<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
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<< " switch (IdxA) {\n"
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<< " default:\n return IdxB;\n";
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for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
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bool Open = false;
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for (unsigned j = 0; j != e; ++j) {
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if (Record *Comp = RegMaps.Composite.lookup(
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std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
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if (!Open) {
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OS << " case " << getQualifiedName(SubRegIndices[i])
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<< ": switch(IdxB) {\n default: return IdxB;\n";
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Open = true;
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}
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OS << " case " << getQualifiedName(SubRegIndices[j])
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<< ": return " << getQualifiedName(Comp) << ";\n";
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}
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}
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if (Open)
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OS << " }\n";
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}
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OS << " }\n}\n\n";
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// Emit the constructor of the class...
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// Emit the constructor of the class...
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OS << ClassName << "::" << ClassName
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OS << ClassName << "::" << ClassName
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<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
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<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
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