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[mips] Add cache and pref instructions
Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210900 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -57,18 +57,24 @@ class MipsDisassembler : public MipsDisassemblerBase {
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public:
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/// Constructor - Initializes the disassembler.
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///
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MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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bool bigEndian) :
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MipsDisassemblerBase(STI, Ctx, bigEndian) {
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IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
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}
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MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
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: MipsDisassemblerBase(STI, Ctx, bigEndian) {
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IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
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}
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bool isMips32r6() const {
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bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
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bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
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bool hasMips32r6() const {
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return STI.getFeatureBits() & Mips::FeatureMips32r6;
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}
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bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
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bool hasCOP3() const {
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// Only present in MIPS-I and MIPS-II
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return !hasMips32() && !hasMips3();
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}
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/// getInstruction - See MCDisassembler.
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DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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@@ -744,7 +750,17 @@ MipsDisassembler::getInstruction(MCInst &instr,
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return MCDisassembler::Fail;
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}
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if (isMips32r6() && isGP64()) {
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if (hasCOP3()) {
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DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
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Result =
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decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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}
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if (hasMips32r6() && isGP64()) {
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DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
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Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
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Address, this, STI);
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@@ -754,7 +770,7 @@ MipsDisassembler::getInstruction(MCInst &instr,
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}
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}
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if (isMips32r6()) {
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if (hasMips32r6()) {
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DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
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Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
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Address, this, STI);
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