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Fix i64->f64 conversion, x86-64, -no-sse. A bit

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tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2010-05-21 00:52:33 +00:00
parent f7d87ee158
commit 7d07b48b26
3 changed files with 45 additions and 0 deletions
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32
lib/Target/X86/X86ISelLowering.cpp
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@ -217,6 +217,11 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
if (!X86ScalarSSEf64) {
setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
if (Subtarget->is64Bit() && Subtarget->hasMMX() && !DisableMMX) {
// Without SSE, i64->f64 goes through memory; i64->MMX is legal.
setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
}
}
// Scalar integer divide and remainder are lowered to use operations that
@ -678,6 +683,14 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v2f32, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
}
}
if (!UseSoftFloat && Subtarget->hasSSE1()) {
@ -7458,6 +7471,24 @@ SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
return DAG.getMergeValues(Ops, 2, dl);
}
SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
SelectionDAG &DAG) const {
EVT SrcVT = Op.getOperand(0).getValueType();
EVT DstVT = Op.getValueType();
assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
Subtarget->hasMMX() && !DisableMMX) &&
"Unexpected custom BIT_CONVERT");
assert((DstVT == MVT::i64 ||
(DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
"Unexpected custom BIT_CONVERT");
// i64 <=> MMX conversions are Legal.
if (SrcVT==MVT::i64 && DstVT.isVector())
return Op;
if (DstVT==MVT::i64 && SrcVT.isVector())
return Op;
// All other conversions need to be expanded.
return SDValue();
}
SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc();
@ -7527,6 +7558,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SMULO:
case ISD::UMULO: return LowerXALUO(Op, DAG);
case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
}
}

1
lib/Target/X86/X86ISelLowering.h
View File

@ -677,6 +677,7 @@ namespace llvm {
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
SelectionDAG &DAG) const;
SDValue LowerBIT_CONVERT(SDValue op, SelectionDAG &DAG) const;
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;

12
test/CodeGen/X86/2010-05-16-nosseconversion.ll Normal file
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@ -0,0 +1,12 @@
; RUN: llc -mtriple=x86_64-apple-darwin -mattr=-sse < %s
; PR 7135
@x = common global i64 0 ; <i64*> [#uses=1]
define i32 @foo() nounwind readonly ssp {
entry:
%0 = load i64* @x, align 8 ; <i64> [#uses=1]
%1 = uitofp i64 %0 to double ; <double> [#uses=1]
%2 = fptosi double %1 to i32 ; <i32> [#uses=1]
ret i32 %2
}