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Turn SelectionDAGBuilder::GetRegistersForValue into a local function.

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It couldn't be used outside of the file because SDISelAsmOperandInfo
is local to SelectionDAGBuilder.cpp. Making it a static function avoids
a weird linkage dance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128342 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2011-03-26 16:35:10 +00:00
parent 050db52276
commit 7d706ede7d
2 changed files with 16 additions and 19 deletions
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30
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -50,7 +50,6 @@
#include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
@ -5202,12 +5201,11 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
LowerCallTo(&I, Callee, I.isTailCall()); LowerCallTo(&I, Callee, I.isTailCall());
} }
namespace llvm { namespace {
/// AsmOperandInfo - This contains information for each constraint that we are /// AsmOperandInfo - This contains information for each constraint that we are
/// lowering. /// lowering.
class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
public TargetLowering::AsmOperandInfo {
public: public:
/// CallOperand - If this is the result output operand or a clobber /// CallOperand - If this is the result output operand or a clobber
/// this is null, otherwise it is the incoming operand to the CallInst. /// this is null, otherwise it is the incoming operand to the CallInst.
@ -5295,7 +5293,7 @@ private:
typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
} // end llvm namespace. } // end anonymous namespace
/// isAllocatableRegister - If the specified register is safe to allocate, /// isAllocatableRegister - If the specified register is safe to allocate,
/// i.e. it isn't a stack pointer or some other special register, return the /// i.e. it isn't a stack pointer or some other special register, return the
@ -5354,11 +5352,13 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF,
/// OpInfo describes the operand. /// OpInfo describes the operand.
/// Input and OutputRegs are the set of already allocated physical registers. /// Input and OutputRegs are the set of already allocated physical registers.
/// ///
void SelectionDAGBuilder:: static void GetRegistersForValue(SelectionDAG &DAG,
GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, const TargetLowering &TLI,
std::set<unsigned> &OutputRegs, DebugLoc DL,
std::set<unsigned> &InputRegs) { SDISelAsmOperandInfo &OpInfo,
LLVMContext &Context = FuncInfo.Fn->getContext(); std::set<unsigned> &OutputRegs,
std::set<unsigned> &InputRegs) {
LLVMContext &Context = *DAG.getContext();
// Compute whether this value requires an input register, an output register, // Compute whether this value requires an input register, an output register,
// or both. // or both.
@ -5404,7 +5404,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// vector types). // vector types).
EVT RegVT = *PhysReg.second->vt_begin(); EVT RegVT = *PhysReg.second->vt_begin();
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
RegVT, OpInfo.CallOperand); RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT; OpInfo.ConstraintVT = RegVT;
} else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
@ -5414,7 +5414,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// machine. // machine.
RegVT = EVT::getIntegerVT(Context, RegVT = EVT::getIntegerVT(Context,
OpInfo.ConstraintVT.getSizeInBits()); OpInfo.ConstraintVT.getSizeInBits());
OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
RegVT, OpInfo.CallOperand); RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT; OpInfo.ConstraintVT = RegVT;
} }
@ -5685,7 +5685,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// If this constraint is for a specific register, allocate it before // If this constraint is for a specific register, allocate it before
// anything else. // anything else.
if (OpInfo.ConstraintType == TargetLowering::C_Register) if (OpInfo.ConstraintType == TargetLowering::C_Register)
GetRegistersForValue(OpInfo, OutputRegs, InputRegs); GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
InputRegs);
} }
// Second pass - Loop over all of the operands, assigning virtual or physregs // Second pass - Loop over all of the operands, assigning virtual or physregs
@ -5696,7 +5697,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// C_Register operands have already been allocated, Other/Memory don't need // C_Register operands have already been allocated, Other/Memory don't need
// to be. // to be.
if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
GetRegistersForValue(OpInfo, OutputRegs, InputRegs); GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
InputRegs);
} }
// AsmNodeOperands - The operands for the ISD::INLINEASM node. // AsmNodeOperands - The operands for the ISD::INLINEASM node.

5
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -60,7 +60,6 @@ class MDNode;
class PHINode; class PHINode;
class PtrToIntInst; class PtrToIntInst;
class ReturnInst; class ReturnInst;
class SDISelAsmOperandInfo;
class SDDbgValue; class SDDbgValue;
class SExtInst; class SExtInst;
class SelectInst; class SelectInst;
@ -380,10 +379,6 @@ public:
assert(N.getNode() == 0 && "Already set a value for this node!"); assert(N.getNode() == 0 && "Already set a value for this node!");
N = NewN; N = NewN;
} }
void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
std::set<unsigned> &OutputRegs,
std::set<unsigned> &InputRegs);
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB,