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ARM64: give NEG priority over SUB when printing aliases.

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For example, the full instruction "sub w0, wzr, w1, uxtw" could print as either
"neg w0, w1" or "sub w0, wzr, w1". The former is better.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208957 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-05-16 09:40:58 +00:00
parent ef5f53b78f
commit 7d80c1a8ac
2 changed files with 21 additions and 23 deletions
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12
lib/Target/ARM64/ARM64InstrFormats.td
View File

@ -1606,12 +1606,6 @@ multiclass AddSub<bit isSub, string mnemonic,
let Inst{31} = 1;
}
// Register/register aliases with no shift when SP is not used.
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
GPR32, GPR32, GPR32, 0>;
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
GPR64, GPR64, GPR64, 0>;
// Register/register aliases with no shift when either the destination or
// first source register is SP. This relies on the shifted register aliases
// above matching first in the case when SP is not used.
@ -1690,12 +1684,6 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs")
XZR, GPR64:$src1, GPR64:$src2, 0)>;
// Register/register aliases with no shift when SP is not used.
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
GPR32, GPR32, GPR32, 0>;
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
GPR64, GPR64, GPR64, 0>;
// Register/register aliases with no shift when the first source register
// is SP. This relies on the shifted register aliases above matching first
// in the case when SP is not used.

32
lib/Target/ARM64/ARM64InstrInfo.td
View File

@ -554,15 +554,6 @@ def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
(ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
}
// FIXME: TableGen can very nearly handle printing all of these, we should make
// it work properly.
def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
def : InstAlias<"neg $dst, $src, $shift",
(SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
def : InstAlias<"neg $dst, $src, $shift",
(SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
// Because of the immediate format for add/sub-imm instructions, the
// expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
// These patterns capture that transformation.
@ -577,13 +568,32 @@ def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
(ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
}
def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
def : InstAlias<"neg $dst, $src$shift",
(SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
def : InstAlias<"neg $dst, $src$shift",
(SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
def : InstAlias<"negs $dst, $src, $shift",
def : InstAlias<"negs $dst, $src$shift",
(SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
def : InstAlias<"negs $dst, $src, $shift",
def : InstAlias<"negs $dst, $src$shift",
(SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
// Register/register aliases with no shift when SP is not used.
def : AddSubRegAlias<"add", ADDWrs, GPR32, GPR32, GPR32, 0>;
def : AddSubRegAlias<"add", ADDXrs, GPR64, GPR64, GPR64, 0>;
def : AddSubRegAlias<"sub", SUBWrs, GPR32, GPR32, GPR32, 0>;
def : AddSubRegAlias<"sub", SUBXrs, GPR64, GPR64, GPR64, 0>;
def : AddSubRegAlias<"adds", ADDSWrs, GPR32, GPR32, GPR32, 0>;
def : AddSubRegAlias<"adds", ADDSXrs, GPR64, GPR64, GPR64, 0>;
def : AddSubRegAlias<"subs", SUBSWrs, GPR32, GPR32, GPR32, 0>;
def : AddSubRegAlias<"subs", SUBSXrs, GPR64, GPR64, GPR64, 0>;
// Unsigned/Signed divide
defm UDIV : Div<0, "udiv", udiv>;
defm SDIV : Div<1, "sdiv", sdiv>;