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[mips] Enable code generation for MIPS-III.

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Summary:
This commit enables the MIPS-III target and adds support for code
generation of SELECT nodes. We have to use pseudo-instructions with
custom inserters for these nodes as MIPS-III CPUs do not have
conditional-move instructions.

Depends on D6212

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224128 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vasileios Kalintiris
2014-12-12 15:16:46 +00:00
parent a4f5a5525d
commit 7db2065236
4 changed files with 163 additions and 102 deletions
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8
lib/Target/Mips/MipsSubtarget.cpp
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@ -129,14 +129,10 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
if (MipsArchVersion == MipsDefault)
MipsArchVersion = Mips32;
// Don't even attempt to generate code for MIPS-I, MIPS-III and MIPS-V.
// They have not been tested and currently exist for the integrated
// assembler only.
// Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
// been tested and currently exist for the integrated assembler only.
if (MipsArchVersion == Mips1)
report_fatal_error("Code generation for MIPS-I is not implemented", false);
if (MipsArchVersion == Mips3)
report_fatal_error("Code generation for MIPS-III is not implemented",
false);
if (MipsArchVersion == Mips5)
report_fatal_error("Code generation for MIPS-V is not implemented", false);