6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-21 18:24:23 +00:00
Code Issues Projects Releases Wiki Activity

Fixed load syntax in EmitAssembly

Browse Source 
Fixed cpReg2Mem (store) operand oreder in SparcRegInfo.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
2001-10-24 22:05:34 +00:00
parent 4a82271451
commit 7dcd61209a
2 changed files with 47 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
lib/Target/SparcV9/SparcV9AsmPrinter.cpp
View File

@ -182,10 +182,47 @@ void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
printOperand(MI->getOperand(1)); printOperand(MI->getOperand(1));
Out << endl; Out << endl;
return; return;
default: break; default: break;
} }
if( Target.getInstrInfo().isLoad(Opcode) ) { // if Load
assert(MI->getNumOperands() == 3 && "Loads must have 3 operands");
Out << "[";
printOperand(MI->getOperand(0));
const MachineOperand& ImmOp = MI->getOperand(1);
if( ImmOp.getImmedValue() >= 0)
Out << "+";
printOperand(ImmOp);
Out << "]";
Out << ", ";
printOperand(MI->getOperand(2));
Out << endl;
return;
}
if( Target.getInstrInfo().isStore(Opcode) ) { // if Store
assert(MI->getNumOperands() == 3 && "Stores must have 3 operands");
printOperand(MI->getOperand(0));
Out << ", ";
Out << "[";
printOperand(MI->getOperand(1));
const MachineOperand& ImmOp = MI->getOperand(2);
if( ImmOp.getImmedValue() >= 0)
Out << "+";
printOperand(ImmOp);
Out << "]";
Out << endl;
return;
}
unsigned Mask = getOperandMask(Opcode); unsigned Mask = getOperandMask(Opcode);
bool NeedComma = false; bool NeedComma = false;

18
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@ -775,8 +775,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// Copy from a register to memory. Register number must be the unified // Copy from a register to memory (i.e., Store). Register number must
// register number // be the unified register number
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
@ -794,24 +794,24 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
case IntCCRegType: case IntCCRegType:
case FloatCCRegType: case FloatCCRegType:
MI = new MachineInstr(STX, 3); MI = new MachineInstr(STX, 3);
MI->SetMachineOperand(0, DestPtrReg, false); MI->SetMachineOperand(0, SrcReg, false);
MI->SetMachineOperand(1, SrcReg, false); MI->SetMachineOperand(1, DestPtrReg, false);
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset, false); (int64_t) Offset, false);
break; break;
case FPSingleRegType: case FPSingleRegType:
MI = new MachineInstr(ST, 3); MI = new MachineInstr(ST, 3);
MI->SetMachineOperand(0, DestPtrReg, false); MI->SetMachineOperand(0, SrcReg, false);
MI->SetMachineOperand(1, SrcReg, false); MI->SetMachineOperand(1, DestPtrReg, false);
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset, false); (int64_t) Offset, false);
break; break;
case FPDoubleRegType: case FPDoubleRegType:
MI = new MachineInstr(STD, 3); MI = new MachineInstr(STD, 3);
MI->SetMachineOperand(0, DestPtrReg, false); MI->SetMachineOperand(0, SrcReg, false);
MI->SetMachineOperand(1, SrcReg, false); MI->SetMachineOperand(1, DestPtrReg, false);
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset, false); (int64_t) Offset, false);
break; break;
@ -825,7 +825,7 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// Copy from memory to a reg. Register number must be the unified // Copy from memory to a reg (i.e., Load) Register number must be the unified
// register number // register number
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------