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Fixed warnings pointed out by clang.

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Next to work on is ARMDisassemblerCore.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100695 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2010-04-07 21:52:48 +00:00
parent 5edca81626
commit 7e4823c51f
1 changed files with 16 additions and 2 deletions
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18
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@@ -524,6 +524,7 @@ static bool DisassembleThumb1LdPC(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded) { unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
(OpInfo[1].RegClass == 0 && (OpInfo[1].RegClass == 0 &&
@@ -621,6 +622,7 @@ static bool DisassembleThumb1LdStSP(MCInst &MI, unsigned Opcode, uint32_t insn,
&& "Invalid opcode"); && "Invalid opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
assert(NumOps >= 3 && assert(NumOps >= 3 &&
OpInfo[0].RegClass == ARM::tGPRRegClassID && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
@@ -648,6 +650,7 @@ static bool DisassembleThumb1AddPCi(MCInst &MI, unsigned Opcode, uint32_t insn,
assert(Opcode == ARM::tADDrPCi && "Invalid opcode"); assert(Opcode == ARM::tADDrPCi && "Invalid opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
(OpInfo[1].RegClass == 0 && (OpInfo[1].RegClass == 0 &&
@@ -672,6 +675,7 @@ static bool DisassembleThumb1AddSPi(MCInst &MI, unsigned Opcode, uint32_t insn,
assert(Opcode == ARM::tADDrSPi && "Invalid opcode"); assert(Opcode == ARM::tADDrSPi && "Invalid opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
assert(NumOps >= 3 && assert(NumOps >= 3 &&
OpInfo[0].RegClass == ARM::tGPRRegClassID && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
@@ -891,6 +895,8 @@ static bool DisassembleThumb1CondBr(MCInst &MI, unsigned Opcode, uint32_t insn,
return true; return true;
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
assert(NumOps == 3 && OpInfo[0].RegClass == 0 && assert(NumOps == 3 && OpInfo[0].RegClass == 0 &&
OpInfo[1].isPredicate() && OpInfo[2].RegClass == ARM::CCRRegClassID OpInfo[1].isPredicate() && OpInfo[2].RegClass == ARM::CCRRegClassID
&& "Exactly 3 operands expected"); && "Exactly 3 operands expected");
@@ -915,6 +921,8 @@ static bool DisassembleThumb1Br(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded) { unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
assert(NumOps == 1 && OpInfo[0].RegClass == 0 && "1 imm operand expected"); assert(NumOps == 1 && OpInfo[0].RegClass == 0 && "1 imm operand expected");
unsigned Imm11 = getT1Imm11(insn); unsigned Imm11 = getT1Imm11(insn);
@@ -1147,6 +1155,8 @@ static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded) { unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
unsigned &OpIdx = NumOpsAdded; unsigned &OpIdx = NumOpsAdded;
OpIdx = 0; OpIdx = 0;
@@ -1201,6 +1211,7 @@ static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode,
uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded) { uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
assert(NumOps >= 4 assert(NumOps >= 4
&& OpInfo[0].RegClass == ARM::GPRRegClassID && OpInfo[0].RegClass == ARM::GPRRegClassID
@@ -1768,6 +1779,7 @@ static bool DisassembleThumb2Ldpci(MCInst &MI, unsigned Opcode,
uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded) { uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false;
assert(NumOps >= 2 && assert(NumOps >= 2 &&
OpInfo[0].RegClass == ARM::GPRRegClassID && OpInfo[0].RegClass == ARM::GPRRegClassID &&
@@ -2174,8 +2186,10 @@ static bool DisassembleThumbFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned bits15_11 = slice(HalfWord, 15, 11); unsigned bits15_11 = slice(HalfWord, 15, 11);
// A6.1 Thumb instruction set encoding // A6.1 Thumb instruction set encoding
assert((bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) && if (!(bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F)) {
"Bits [15:11] of first halfword of a Thumb2 instruction out of range"); assert("Bits[15:11] first halfword of Thumb2 instruction is out of range");
return false;
}
// A6.3 32-bit Thumb instruction encoding // A6.3 32-bit Thumb instruction encoding