mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-09-24 23:28:41 +00:00
MEGAPATCH checkin.
For details, See: docs/2002-06-25-MegaPatchInfo.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2779 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
@@ -1489,18 +1489,17 @@ namespace {
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AU.addRequired(FunctionLiveVarInfo::ID);
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}
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bool runOnFunction(Function *F);
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bool runOnFunction(Function &F);
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};
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} // end anonymous namespace
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bool
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InstructionSchedulingWithSSA::runOnFunction(Function *M)
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bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
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{
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if (SchedDebugLevel == Sched_Disable)
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return false;
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SchedGraphSet graphSet(M, target);
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SchedGraphSet graphSet(&F, target);
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if (SchedDebugLevel >= Sched_PrintSchedGraphs)
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{
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@@ -1520,7 +1519,7 @@ InstructionSchedulingWithSSA::runOnFunction(Function *M)
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cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
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// expensive!
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SchedPriorities schedPrio(M, graph,getAnalysis<FunctionLiveVarInfo>());
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SchedPriorities schedPrio(&F, graph,getAnalysis<FunctionLiveVarInfo>());
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SchedulingManager S(target, graph, schedPrio);
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ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
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@@ -1533,7 +1532,7 @@ InstructionSchedulingWithSSA::runOnFunction(Function *M)
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if (SchedDebugLevel >= Sched_PrintMachineCode)
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{
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cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
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MachineCodeForMethod::get(M).dump();
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MachineCodeForMethod::get(&F).dump();
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}
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return false;
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@@ -985,7 +985,7 @@ SchedGraphSet::buildGraphsForMethod(const Function *F,
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const TargetMachine& target)
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{
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for (Function::const_iterator BI = F->begin(); BI != F->end(); ++BI)
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addGraph(new SchedGraph(*BI, target));
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addGraph(new SchedGraph(BI, target));
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}
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@@ -84,29 +84,20 @@ void LiveRangeInfo::constructLiveRanges() {
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// first find the live ranges for all incoming args of the function since
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// those LRs start from the start of the function
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// get the argument list
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const Function::ArgumentListType& ArgList = Meth->getArgumentList();
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Function::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
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LiveRange * ArgRange = new LiveRange(); // creates a new LR and
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const Value *Val = (const Value *) *ArgIt;
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ArgRange->insert(Val); // add the arg (def) to it
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LiveRangeMap[Val] = ArgRange;
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for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI){
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LiveRange *ArgRange = new LiveRange(); // creates a new LR and
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ArgRange->insert(AI); // add the arg (def) to it
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LiveRangeMap[AI] = ArgRange;
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// create a temp machine op to find the register class of value
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//const MachineOperand Op(MachineOperand::MO_VirtualRegister);
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unsigned rcid = MRI.getRegClassIDOfValue( Val );
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ArgRange->setRegClass(RegClassList[ rcid ] );
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unsigned rcid = MRI.getRegClassIDOfValue(AI);
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ArgRange->setRegClass(RegClassList[rcid]);
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if( DEBUG_RA > 1) {
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cerr << " adding LiveRange for argument "
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<< RAV((const Value *)*ArgIt) << "\n";
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}
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if( DEBUG_RA > 1)
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cerr << " adding LiveRange for argument " << RAV(AI) << "\n";
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}
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// Now suggest hardware registers for these function args
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@@ -123,7 +114,7 @@ void LiveRangeInfo::constructLiveRanges() {
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// the same Value in machine instructions.
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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const MachineCodeForBasicBlock& MIVec = BBI->getMachineInstrVec();
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// iterate over all the machine instructions in BB
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for(MachineCodeForBasicBlock::const_iterator MInstIterator = MIVec.begin();
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@@ -275,7 +266,7 @@ void LiveRangeInfo::coalesceLRs()
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BBI != BBE; ++BBI) {
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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const MachineCodeForBasicBlock& MIVec = BBI->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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@@ -49,12 +49,11 @@ namespace {
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const char *getPassName() const { return "Register Allocation"; }
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bool runOnFunction(Function *F) {
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bool runOnFunction(Function &F) {
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if (DEBUG_RA)
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cerr << "\n******************** Function "<< F->getName()
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<< " ********************\n";
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cerr << "\n********* Function "<< F.getName() << " ***********\n";
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PhyRegAlloc PRA(F, Target, &getAnalysis<FunctionLiveVarInfo>(),
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PhyRegAlloc PRA(&F, Target, &getAnalysis<FunctionLiveVarInfo>(),
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&getAnalysis<LoopInfo>());
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PRA.allocateRegisters();
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@@ -87,7 +86,7 @@ PhyRegAlloc::PhyRegAlloc(Function *F, const TargetMachine& tm,
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// create each RegisterClass and put in RegClassList
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//
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for(unsigned int rc=0; rc < NumOfRegClasses; rc++)
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for (unsigned rc=0; rc < NumOfRegClasses; rc++)
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RegClassList.push_back(new RegClass(F, MRI.getMachineRegClass(rc),
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&ResColList));
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}
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@@ -97,7 +96,7 @@ PhyRegAlloc::PhyRegAlloc(Function *F, const TargetMachine& tm,
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// Destructor: Deletes register classes
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//----------------------------------------------------------------------------
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PhyRegAlloc::~PhyRegAlloc() {
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
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for ( unsigned rc=0; rc < NumOfRegClasses; rc++)
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delete RegClassList[rc];
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AddedInstrMap.clear();
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@@ -120,7 +119,7 @@ void PhyRegAlloc::createIGNodeListsAndIGs() {
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if (HMI->first) {
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LiveRange *L = HMI->second; // get the LiveRange
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if (!L) {
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if( DEBUG_RA) {
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if (DEBUG_RA) {
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cerr << "\n*?!?Warning: Null liver range found for: "
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<< RAV(HMI->first) << "\n";
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}
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@@ -128,7 +127,7 @@ void PhyRegAlloc::createIGNodeListsAndIGs() {
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}
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// if the Value * is not null, and LR
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// is not yet written to the IGNodeList
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if( !(L->getUserIGNode()) ) {
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if (!(L->getUserIGNode()) ) {
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RegClass *const RC = // RegClass of first value in the LR
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RegClassList[ L->getRegClass()->getID() ];
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@@ -138,10 +137,10 @@ void PhyRegAlloc::createIGNodeListsAndIGs() {
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}
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// init RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[rc]->createInterferenceGraph();
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if( DEBUG_RA)
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if (DEBUG_RA)
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cerr << "LRLists Created!\n";
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}
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@@ -171,7 +170,7 @@ void PhyRegAlloc::addInterference(const Value *Def,
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// for each live var in live variable set
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//
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for( ; LIt != LVSet->end(); ++LIt) {
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for ( ; LIt != LVSet->end(); ++LIt) {
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if (DEBUG_RA > 1)
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cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
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@@ -184,7 +183,7 @@ void PhyRegAlloc::addInterference(const Value *Def,
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// doesn't have a dominating def - see Assumptions above
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//
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if (LROfVar) {
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if(LROfDef == LROfVar) // do not set interf for same LR
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if (LROfDef == LROfVar) // do not set interf for same LR
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continue;
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// if 2 reg classes are the same set interference
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@@ -212,20 +211,20 @@ void PhyRegAlloc::addInterference(const Value *Def,
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void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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const ValueSet *LVSetAft) {
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if( DEBUG_RA)
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if (DEBUG_RA)
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cerr << "\n For call inst: " << *MInst;
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ValueSet::const_iterator LIt = LVSetAft->begin();
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// for each live var in live variable set after machine inst
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//
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for( ; LIt != LVSetAft->end(); ++LIt) {
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for ( ; LIt != LVSetAft->end(); ++LIt) {
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// get the live range corresponding to live var
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//
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LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
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if( LR && DEBUG_RA) {
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if (LR && DEBUG_RA) {
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cerr << "\n\tLR Aft Call: ";
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printSet(*LR);
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}
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@@ -233,9 +232,9 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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// LR can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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//
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if( LR ) {
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if (LR ) {
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LR->setCallInterference();
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if( DEBUG_RA) {
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if (DEBUG_RA) {
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cerr << "\n ++Added call interf for LR: " ;
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printSet(*LR);
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}
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@@ -259,7 +258,7 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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// If the CALL is an indirect call, find the LR of the function pointer.
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// That has a call interference because it conflicts with outgoing args.
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if( const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
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if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
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LiveRange *AddrValLR = LRI.getLiveRangeForValue( AddrVal );
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assert( AddrValLR && "No LR for indirect addr val of call");
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AddrValLR->setCallInterference();
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@@ -278,7 +277,7 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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if(DEBUG_RA) cerr << "Creating interference graphs ...\n";
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if (DEBUG_RA) cerr << "Creating interference graphs ...\n";
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unsigned BBLoopDepthCost;
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for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
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@@ -286,26 +285,26 @@ void PhyRegAlloc::buildInterferenceGraphs()
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// find the 10^(loop_depth) of this BB
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//
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BBLoopDepthCost = (unsigned) pow(10.0, LoopDepthCalc->getLoopDepth(*BBI));
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BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BBI));
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// get the iterator for machine instructions
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//
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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const MachineCodeForBasicBlock& MIVec = BBI->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator MII = MIVec.begin();
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// iterate over all the machine instructions in BB
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//
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for( ; MII != MIVec.end(); ++MII) {
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for ( ; MII != MIVec.end(); ++MII) {
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const MachineInstr *MInst = *MII;
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// get the LV set after the instruction
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//
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const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, *BBI);
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const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BBI);
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const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
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if( isCallInst ) {
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if (isCallInst ) {
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// set the isCallInterference flag of each live range wich extends
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// accross this call instruction. This information is used by graph
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// coloring algo to avoid allocating volatile colors to live ranges
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@@ -339,9 +338,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
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// instr (currently, only calls have this).
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//
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unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
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if( NumOfImpRefs > 0 ) {
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for(unsigned z=0; z < NumOfImpRefs; z++)
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if( MInst->implicitRefIsDefined(z) )
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if ( NumOfImpRefs > 0 ) {
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for (unsigned z=0; z < NumOfImpRefs; z++)
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if (MInst->implicitRefIsDefined(z) )
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addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
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}
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@@ -355,7 +354,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
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//
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addInterferencesForArgs();
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if( DEBUG_RA)
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if (DEBUG_RA)
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cerr << "Interference graphs calculted!\n";
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}
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@@ -380,14 +379,14 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
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assert((LROfOp1 || !It1.isDef()) && "No LR for Def in PSEUDO insruction");
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MachineInstr::const_val_op_iterator It2 = It1;
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for(++It2; It2 != ItE; ++It2) {
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for (++It2; It2 != ItE; ++It2) {
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const LiveRange *LROfOp2 = LRI.getLiveRangeForValue(*It2);
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if (LROfOp2) {
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RegClass *RCOfOp1 = LROfOp1->getRegClass();
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RegClass *RCOfOp2 = LROfOp2->getRegClass();
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if( RCOfOp1 == RCOfOp2 ){
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if (RCOfOp1 == RCOfOp2 ){
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RCOfOp1->setInterference( LROfOp1, LROfOp2 );
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setInterf = true;
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}
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@@ -409,21 +408,14 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterferencesForArgs() {
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// get the InSet of root BB
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const ValueSet &InSet = LVI->getInSetOfBB(Meth->front());
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const ValueSet &InSet = LVI->getInSetOfBB(&Meth->front());
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// get the argument list
|
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const Function::ArgumentListType &ArgList = Meth->getArgumentList();
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// get an iterator to arg list
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Function::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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|
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|
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for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
|
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addInterference((Value*)*ArgIt, &InSet, false);// add interferences between
|
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// args and LVars at start
|
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if( DEBUG_RA > 1)
|
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cerr << " - %% adding interference for argument "
|
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<< RAV((const Value *)*ArgIt) << "\n";
|
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for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI) {
|
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// add interferences between args and LVars at start
|
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addInterference(AI, &InSet, false);
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|
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if (DEBUG_RA > 1)
|
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cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
|
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}
|
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}
|
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|
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@@ -472,9 +464,9 @@ AppendInstructions(std::vector<MachineInstr *> &IAft,
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{
|
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MachineInstr* OrigMI = *MII;
|
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std::vector<MachineInstr *>::iterator AdIt;
|
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for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
|
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for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
|
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{
|
||||
if(DEBUG_RA) {
|
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if (DEBUG_RA) {
|
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if (OrigMI) cerr << "For MInst: " << *OrigMI;
|
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cerr << msg << " APPENDed instr: " << **AdIt << "\n";
|
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}
|
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@@ -487,25 +479,22 @@ AppendInstructions(std::vector<MachineInstr *> &IAft,
|
||||
|
||||
void PhyRegAlloc::updateMachineCode()
|
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{
|
||||
const BasicBlock* entryBB = Meth->getEntryNode();
|
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if (entryBB) {
|
||||
MachineCodeForBasicBlock& MIVec = entryBB->getMachineInstrVec();
|
||||
MachineCodeForBasicBlock::iterator MII = MIVec.begin();
|
||||
MachineCodeForBasicBlock& MIVec = Meth->getEntryNode().getMachineInstrVec();
|
||||
|
||||
// Insert any instructions needed at method entry
|
||||
PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MIVec, MII,
|
||||
"At function entry: \n");
|
||||
assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
|
||||
"InstrsAfter should be unnecessary since we are just inserting at "
|
||||
"the function entry point here.");
|
||||
}
|
||||
// Insert any instructions needed at method entry
|
||||
MachineCodeForBasicBlock::iterator MII = MIVec.begin();
|
||||
PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MIVec, MII,
|
||||
"At function entry: \n");
|
||||
assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
|
||||
"InstrsAfter should be unnecessary since we are just inserting at "
|
||||
"the function entry point here.");
|
||||
|
||||
for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
|
||||
BBI != BBE; ++BBI) {
|
||||
|
||||
// iterate over all the machine instructions in BB
|
||||
MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
||||
for(MachineCodeForBasicBlock::iterator MII = MIVec.begin();
|
||||
MachineCodeForBasicBlock &MIVec = BBI->getMachineInstrVec();
|
||||
for (MachineCodeForBasicBlock::iterator MII = MIVec.begin();
|
||||
MII != MIVec.end(); ++MII) {
|
||||
|
||||
MachineInstr *MInst = *MII;
|
||||
@@ -530,7 +519,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
mcInfo.popAllTempValues(TM);
|
||||
|
||||
if (TM.getInstrInfo().isCall(Opcode))
|
||||
MRI.colorCallArgs(MInst, LRI, &AI, *this, *BBI);
|
||||
MRI.colorCallArgs(MInst, LRI, &AI, *this, BBI);
|
||||
else if (TM.getInstrInfo().isReturn(Opcode))
|
||||
MRI.colorRetValue(MInst, LRI, &AI);
|
||||
}
|
||||
@@ -540,7 +529,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
|
||||
// if this machine instr is call, insert caller saving code
|
||||
|
||||
if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
|
||||
if ((TM.getInstrInfo()).isCall( MInst->getOpCode()) )
|
||||
MRI.insertCallerSavingCode(MInst, *BBI, *this );
|
||||
|
||||
*/
|
||||
@@ -551,22 +540,22 @@ void PhyRegAlloc::updateMachineCode()
|
||||
// mcInfo.popAllTempValues(TM);
|
||||
// TODO ** : do later
|
||||
|
||||
//for(MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) {
|
||||
//for (MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) {
|
||||
|
||||
|
||||
// Now replace set the registers for operands in the machine instruction
|
||||
//
|
||||
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
||||
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
||||
|
||||
MachineOperand& Op = MInst->getOperand(OpNum);
|
||||
|
||||
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
Op.getOperandType() == MachineOperand::MO_CCRegister) {
|
||||
|
||||
const Value *const Val = Op.getVRegValue();
|
||||
|
||||
// delete this condition checking later (must assert if Val is null)
|
||||
if( !Val) {
|
||||
if (!Val) {
|
||||
if (DEBUG_RA)
|
||||
cerr << "Warning: NULL Value found for operand\n";
|
||||
continue;
|
||||
@@ -575,7 +564,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
|
||||
LiveRange *const LR = LRI.getLiveRangeForValue(Val);
|
||||
|
||||
if ( !LR ) {
|
||||
if (!LR ) {
|
||||
|
||||
// nothing to worry if it's a const or a label
|
||||
|
||||
@@ -586,7 +575,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
}
|
||||
|
||||
// if register is not allocated, mark register as invalid
|
||||
if( Op.getAllocatedRegNum() == -1)
|
||||
if (Op.getAllocatedRegNum() == -1)
|
||||
Op.setRegForValue( MRI.getInvalidRegNum());
|
||||
|
||||
|
||||
@@ -595,7 +584,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
|
||||
unsigned RCID = (LR->getRegClass())->getID();
|
||||
|
||||
if( LR->hasColor() ) {
|
||||
if (LR->hasColor() ) {
|
||||
Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
|
||||
}
|
||||
else {
|
||||
@@ -604,7 +593,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
// for spilled opeands in this machine instruction
|
||||
|
||||
//assert(0 && "LR must be spilled");
|
||||
insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
|
||||
insertCode4SpilledLR(LR, MInst, BBI, OpNum );
|
||||
|
||||
}
|
||||
}
|
||||
@@ -620,7 +609,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
// If there are instructions to be added, *before* this machine
|
||||
// instruction, add them now.
|
||||
//
|
||||
if(AddedInstrMap.count(MInst)) {
|
||||
if (AddedInstrMap.count(MInst)) {
|
||||
PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MIVec, MII,"");
|
||||
}
|
||||
|
||||
@@ -638,7 +627,7 @@ void PhyRegAlloc::updateMachineCode()
|
||||
if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
|
||||
move2DelayedInstr(MInst, *(MII+delay) );
|
||||
|
||||
if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
|
||||
if (DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
|
||||
}
|
||||
|
||||
else {
|
||||
@@ -698,10 +687,10 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
|
||||
AI.InstrnsBefore.insert(AI.InstrnsBefore.end(),
|
||||
AdIMid.begin(), AdIMid.end());
|
||||
|
||||
if(MIBef)
|
||||
if (MIBef)
|
||||
AI.InstrnsBefore.push_back(MIBef);
|
||||
|
||||
if(MIAft)
|
||||
if (MIAft)
|
||||
AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft);
|
||||
|
||||
} else { // if this is a Def
|
||||
@@ -722,14 +711,16 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
|
||||
|
||||
} // if !DEF
|
||||
|
||||
cerr << "\nFor Inst " << *MInst;
|
||||
cerr << " - SPILLED LR: "; printSet(*LR);
|
||||
cerr << "\n - Added Instructions:";
|
||||
if (MIBef) cerr << *MIBef;
|
||||
for (vector<MachineInstr*>::const_iterator II=AdIMid.begin();
|
||||
II != AdIMid.end(); ++II)
|
||||
cerr << **II;
|
||||
if (MIAft) cerr << *MIAft;
|
||||
if (DEBUG_RA) {
|
||||
cerr << "\nFor Inst " << *MInst;
|
||||
cerr << " - SPILLED LR: "; printSet(*LR);
|
||||
cerr << "\n - Added Instructions:";
|
||||
if (MIBef) cerr << *MIBef;
|
||||
for (vector<MachineInstr*>::const_iterator II=AdIMid.begin();
|
||||
II != AdIMid.end(); ++II)
|
||||
cerr << **II;
|
||||
if (MIAft) cerr << *MIAft;
|
||||
}
|
||||
|
||||
Op.setRegForValue(TmpRegU); // set the opearnd
|
||||
}
|
||||
@@ -755,7 +746,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(RegClass *RC,
|
||||
int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
|
||||
|
||||
|
||||
if( RegU != -1) {
|
||||
if (RegU != -1) {
|
||||
// we found an unused register, so we can simply use it
|
||||
MIBef = MIAft = NULL;
|
||||
}
|
||||
@@ -799,20 +790,20 @@ int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
|
||||
|
||||
std::vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
|
||||
|
||||
for(unsigned i=0; i < NumAvailRegs; i++) // Reset array
|
||||
for (unsigned i=0; i < NumAvailRegs; i++) // Reset array
|
||||
IsColorUsedArr[i] = false;
|
||||
|
||||
ValueSet::const_iterator LIt = LVSetBef->begin();
|
||||
|
||||
// for each live var in live variable set after machine inst
|
||||
for( ; LIt != LVSetBef->end(); ++LIt) {
|
||||
for ( ; LIt != LVSetBef->end(); ++LIt) {
|
||||
|
||||
// get the live range corresponding to live var
|
||||
LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
|
||||
|
||||
// LR can be null if it is a const since a const
|
||||
// doesn't have a dominating def - see Assumptions above
|
||||
if( LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor() )
|
||||
if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor() )
|
||||
IsColorUsedArr[ LRofLV->getColor() ] = true;
|
||||
}
|
||||
|
||||
@@ -822,7 +813,7 @@ int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
|
||||
|
||||
setRelRegsUsedByThisInst(RC, MInst);
|
||||
|
||||
for(unsigned c=0; c < NumAvailRegs; c++) // find first unused color
|
||||
for (unsigned c=0; c < NumAvailRegs; c++) // find first unused color
|
||||
if (!IsColorUsedArr[c])
|
||||
return MRI.getUnifiedRegNum(RC->getID(), c);
|
||||
|
||||
@@ -841,12 +832,12 @@ int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
|
||||
unsigned NumAvailRegs = RC->getNumOfAvailRegs();
|
||||
|
||||
|
||||
for(unsigned i=0; i < NumAvailRegs ; i++) // Reset array
|
||||
for (unsigned i=0; i < NumAvailRegs ; i++) // Reset array
|
||||
IsColorUsedArr[i] = false;
|
||||
|
||||
setRelRegsUsedByThisInst(RC, MInst);
|
||||
|
||||
for(unsigned c=0; c < RC->getNumOfAvailRegs(); c++)// find first unused color
|
||||
for (unsigned c=0; c < RC->getNumOfAvailRegs(); c++)// find first unused color
|
||||
if (!IsColorUsedArr[c])
|
||||
return MRI.getUnifiedRegNum(RC->getID(), c);
|
||||
|
||||
@@ -865,19 +856,19 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
|
||||
|
||||
vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
|
||||
|
||||
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
||||
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
||||
|
||||
const MachineOperand& Op = MInst->getOperand(OpNum);
|
||||
|
||||
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
Op.getOperandType() == MachineOperand::MO_CCRegister ) {
|
||||
|
||||
const Value *const Val = Op.getVRegValue();
|
||||
|
||||
if( Val )
|
||||
if( MRI.getRegClassIDOfValue(Val) == RC->getID() ) {
|
||||
if (Val )
|
||||
if (MRI.getRegClassIDOfValue(Val) == RC->getID() ) {
|
||||
int Reg;
|
||||
if( (Reg=Op.getAllocatedRegNum()) != -1) {
|
||||
if ((Reg=Op.getAllocatedRegNum()) != -1) {
|
||||
IsColorUsedArr[Reg] = true;
|
||||
}
|
||||
else {
|
||||
@@ -885,8 +876,8 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
|
||||
// a register but it has a LR and that received a color
|
||||
|
||||
LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
|
||||
if( LROfVal)
|
||||
if( LROfVal->hasColor() )
|
||||
if (LROfVal)
|
||||
if (LROfVal->hasColor() )
|
||||
IsColorUsedArr[LROfVal->getColor()] = true;
|
||||
}
|
||||
|
||||
@@ -900,12 +891,12 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
|
||||
|
||||
// If there are implicit references, mark them as well
|
||||
|
||||
for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
|
||||
for (unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
|
||||
|
||||
LiveRange *const LRofImpRef =
|
||||
LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
|
||||
|
||||
if(LRofImpRef && LRofImpRef->hasColor())
|
||||
if (LRofImpRef && LRofImpRef->hasColor())
|
||||
IsColorUsedArr[LRofImpRef->getColor()] = true;
|
||||
}
|
||||
}
|
||||
@@ -957,35 +948,35 @@ void PhyRegAlloc::printMachineCode()
|
||||
|
||||
for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
|
||||
BBI != BBE; ++BBI) {
|
||||
cerr << "\n"; printLabel(*BBI); cerr << ": ";
|
||||
cerr << "\n"; printLabel(BBI); cerr << ": ";
|
||||
|
||||
// get the iterator for machine instructions
|
||||
MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
||||
MachineCodeForBasicBlock& MIVec = BBI->getMachineInstrVec();
|
||||
MachineCodeForBasicBlock::iterator MII = MIVec.begin();
|
||||
|
||||
// iterate over all the machine instructions in BB
|
||||
for( ; MII != MIVec.end(); ++MII) {
|
||||
for ( ; MII != MIVec.end(); ++MII) {
|
||||
MachineInstr *const MInst = *MII;
|
||||
|
||||
cerr << "\n\t";
|
||||
cerr << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
||||
|
||||
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
||||
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
||||
MachineOperand& Op = MInst->getOperand(OpNum);
|
||||
|
||||
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
Op.getOperandType() == MachineOperand::MO_CCRegister /*||
|
||||
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
|
||||
|
||||
const Value *const Val = Op.getVRegValue () ;
|
||||
// ****this code is temporary till NULL Values are fixed
|
||||
if( ! Val ) {
|
||||
if (! Val ) {
|
||||
cerr << "\t<*NULL*>";
|
||||
continue;
|
||||
}
|
||||
|
||||
// if a label or a constant
|
||||
if(isa<BasicBlock>(Val)) {
|
||||
if (isa<BasicBlock>(Val)) {
|
||||
cerr << "\t"; printLabel( Op.getVRegValue () );
|
||||
} else {
|
||||
// else it must be a register value
|
||||
@@ -997,17 +988,17 @@ void PhyRegAlloc::printMachineCode()
|
||||
else
|
||||
cerr << "(" << Val << ")";
|
||||
|
||||
if( Op.opIsDef() )
|
||||
if (Op.opIsDef() )
|
||||
cerr << "*";
|
||||
|
||||
const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
|
||||
if( LROfVal )
|
||||
if( LROfVal->hasSpillOffset() )
|
||||
if (LROfVal )
|
||||
if (LROfVal->hasSpillOffset() )
|
||||
cerr << "$";
|
||||
}
|
||||
|
||||
}
|
||||
else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
||||
else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
||||
cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
|
||||
}
|
||||
|
||||
@@ -1018,10 +1009,10 @@ void PhyRegAlloc::printMachineCode()
|
||||
|
||||
|
||||
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
|
||||
if( NumOfImpRefs > 0) {
|
||||
if (NumOfImpRefs > 0) {
|
||||
cerr << "\tImplicit:";
|
||||
|
||||
for(unsigned z=0; z < NumOfImpRefs; z++)
|
||||
for (unsigned z=0; z < NumOfImpRefs; z++)
|
||||
cerr << RAV(MInst->getImplicitRef(z)) << "\t";
|
||||
}
|
||||
|
||||
@@ -1047,7 +1038,7 @@ void PhyRegAlloc::colorCallRetArgs()
|
||||
CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
|
||||
CallRetInstrListType::const_iterator It = CallRetInstList.begin();
|
||||
|
||||
for( ; It != CallRetInstList.end(); ++It ) {
|
||||
for ( ; It != CallRetInstList.end(); ++It ) {
|
||||
|
||||
const MachineInstr *const CRMI = *It;
|
||||
unsigned OpCode = CRMI->getOpCode();
|
||||
@@ -1076,8 +1067,8 @@ void PhyRegAlloc::colorCallRetArgs()
|
||||
//----------------------------------------------------------------------------
|
||||
void PhyRegAlloc::colorIncomingArgs()
|
||||
{
|
||||
const BasicBlock *const FirstBB = Meth->front();
|
||||
const MachineInstr *FirstMI = FirstBB->getMachineInstrVec().front();
|
||||
const BasicBlock &FirstBB = Meth->front();
|
||||
const MachineInstr *FirstMI = FirstBB.getMachineInstrVec().front();
|
||||
assert(FirstMI && "No machine instruction in entry BB");
|
||||
|
||||
MRI.colorMethodArgs(Meth, LRI, &AddedInstrAtEntry);
|
||||
@@ -1104,19 +1095,19 @@ void PhyRegAlloc::printLabel(const Value *const Val) {
|
||||
|
||||
void PhyRegAlloc::markUnusableSugColors()
|
||||
{
|
||||
if(DEBUG_RA ) cerr << "\nmarking unusable suggested colors ...\n";
|
||||
if (DEBUG_RA ) cerr << "\nmarking unusable suggested colors ...\n";
|
||||
|
||||
// hash map iterator
|
||||
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
||||
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
||||
|
||||
for(; HMI != HMIEnd ; ++HMI ) {
|
||||
for (; HMI != HMIEnd ; ++HMI ) {
|
||||
if (HMI->first) {
|
||||
LiveRange *L = HMI->second; // get the LiveRange
|
||||
if (L) {
|
||||
if(L->hasSuggestedColor()) {
|
||||
if (L->hasSuggestedColor()) {
|
||||
int RCID = L->getRegClass()->getID();
|
||||
if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
|
||||
if (MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
|
||||
L->isCallInterference() )
|
||||
L->setSuggestedColorUsable( false );
|
||||
else
|
||||
@@ -1142,7 +1133,7 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
|
||||
LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
|
||||
LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
|
||||
|
||||
for( ; HMI != HMIEnd ; ++HMI) {
|
||||
for ( ; HMI != HMIEnd ; ++HMI) {
|
||||
if (HMI->first && HMI->second) {
|
||||
LiveRange *L = HMI->second; // get the LiveRange
|
||||
if (!L->hasColor()) // NOTE: ** allocating the size of long Type **
|
||||
@@ -1176,25 +1167,25 @@ void PhyRegAlloc::allocateRegisters()
|
||||
|
||||
if (DEBUG_RA) {
|
||||
// print all LRs in all reg classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIGNodeList();
|
||||
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[rc]->printIGNodeList();
|
||||
|
||||
// print IGs in all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIG();
|
||||
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[rc]->printIG();
|
||||
}
|
||||
|
||||
|
||||
LRI.coalesceLRs(); // coalesce all live ranges
|
||||
|
||||
|
||||
if( DEBUG_RA) {
|
||||
if (DEBUG_RA) {
|
||||
// print all LRs in all reg classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIGNodeList();
|
||||
|
||||
// print IGs in all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIG();
|
||||
}
|
||||
|
||||
@@ -1206,7 +1197,7 @@ void PhyRegAlloc::allocateRegisters()
|
||||
markUnusableSugColors();
|
||||
|
||||
// color all register classes using the graph coloring algo
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->colorAllRegs();
|
||||
|
||||
// Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
|
||||
|
||||
Reference in New Issue
Block a user