6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-29 10:32:47 +00:00
Code Issues Projects Releases Wiki Activity

X86FastISel support for loading and storing values of type i1.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80186 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-08-27 00:31:47 +00:00
parent cbbea0ffc7
commit 7e7f06e70a
2 changed files with 24 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/X86/X86FastISel.cpp
View File

@ -195,6 +195,7 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
const TargetRegisterClass *RC = NULL;
switch (VT.getSimpleVT().SimpleTy) {
default: return false;
case MVT::i1:
case MVT::i8:
Opc = X86::MOV8rm;
RC = X86::GR8RegisterClass;
@ -252,6 +253,14 @@ X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
switch (VT.getSimpleVT().SimpleTy) {
case MVT::f80: // No f80 support yet.
default: return false;
case MVT::i1: {
// Mask out all but lowest bit.
unsigned AndResult = createResultReg(X86::GR8RegisterClass);
BuildMI(MBB, DL,
TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
Val = AndResult;
}
// FALLTHROUGH, handling i1 as i8.
case MVT::i8: Opc = X86::MOV8mr; break;
case MVT::i16: Opc = X86::MOV16mr; break;
case MVT::i32: Opc = X86::MOV32mr; break;
@ -277,8 +286,10 @@ bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val,
// If this is a store of a simple constant, fold the constant into the store.
if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
unsigned Opc = 0;
bool Signed = true;
switch (VT.getSimpleVT().SimpleTy) {
default: break;
case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
case MVT::i8: Opc = X86::MOV8mi; break;
case MVT::i16: Opc = X86::MOV16mi; break;
case MVT::i32: Opc = X86::MOV32mi; break;
@ -291,7 +302,8 @@ bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val,
if (Opc) {
addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
.addImm(CI->getSExtValue());
.addImm(Signed ? CI->getSExtValue() :
CI->getZExtValue());
return true;
}
}
@ -606,7 +618,7 @@ bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) {
/// X86SelectStore - Select and emit code to implement store instructions.
bool X86FastISel::X86SelectStore(Instruction* I) {
EVT VT;
if (!isTypeLegal(I->getOperand(0)->getType(), VT))
if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
return false;
X86AddressMode AM;
@ -620,7 +632,7 @@ bool X86FastISel::X86SelectStore(Instruction* I) {
///
bool X86FastISel::X86SelectLoad(Instruction *I) {
EVT VT;
if (!isTypeLegal(I->getType(), VT))
if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
return false;
X86AddressMode AM;

9
test/CodeGen/X86/fast-isel.ll
View File

@ -64,3 +64,12 @@ define i8* @inttoptr_i32(i32 %p) nounwind {
%t = inttoptr i32 %p to i8*
ret i8* %t
}
define void @store_i1(i1* %p, i1 %t) nounwind {
store i1 %t, i1* %p
ret void
}
define i1 @load_i1(i1* %p) nounwind {
%t = load i1* %p
ret i1 %t
}