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Match getTargetNode() changes (now return SDNode* instead of SDOperand).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26085 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-02-09 07:17:49 +00:00
parent d7805a741d
commit 7e9b26fc73
5 changed files with 247 additions and 206 deletions
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75
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -194,10 +194,11 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Chain.getValue(1)); Chain.getValue(1));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
Chain.getValue(1)); Chain.getValue(1));
Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, SDNode *CNode =
Chain, Chain.getValue(1)); CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
Chain, Chain.getValue(1));
Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
Chain.getValue(1)); SDOperand(CNode, 1));
Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain); Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
return; return;
} }
@ -255,10 +256,11 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
MachineConstantPool *CP = BB->getParent()->getConstantPool(); MachineConstantPool *CP = BB->getParent()->getConstantPool();
ConstantUInt *C = ConstantUInt *C =
ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval); ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64); SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg()); SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
getGlobalBaseReg());
Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
CPI, Tmp, CurDAG->getEntryNode()); CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
return; return;
} }
case ISD::TargetConstantFP: { case ISD::TargetConstantFP: {
@ -299,30 +301,31 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDOperand tmp1, tmp2; SDOperand tmp1, tmp2;
Select(tmp1, N->getOperand(0)); Select(tmp1, N->getOperand(0));
Select(tmp2, N->getOperand(1)); Select(tmp2, N->getOperand(1));
SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64, SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
rev?tmp2:tmp1, rev?tmp2:tmp1,
rev?tmp1:tmp2); rev?tmp1:tmp2);
if (isNE) if (isNE)
cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp, cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
CurDAG->getRegister(Alpha::F31, MVT::f64)); CurDAG->getRegister(Alpha::F31, MVT::f64));
SDOperand LD; SDOperand LD;
if (AlphaLowering.hasITOF()) { if (AlphaLowering.hasITOF()) {
LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp); LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
} else { } else {
int FrameIdx = int FrameIdx =
CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64); SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other, SDOperand ST =
cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)); SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other,
LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI, SDOperand(cmp, 0), FI,
CurDAG->getRegister(Alpha::R31, MVT::i64), CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
ST); LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
CurDAG->getRegister(Alpha::R31, MVT::i64),
ST), 0);
} }
SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
CurDAG->getRegister(Alpha::R31, MVT::i64), CurDAG->getRegister(Alpha::R31, MVT::i64),
LD); LD), 0);
Result = FP;
return; return;
} }
break; break;
@ -347,15 +350,15 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
int FrameIdx = int FrameIdx =
CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64); SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other, SDOperand ST =
cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)); SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI, cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
CurDAG->getRegister(Alpha::R31, MVT::i64), LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
ST); CurDAG->getRegister(Alpha::R31, MVT::i64),
ST), 0);
} }
SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
MVT::f64, FV, TV, LD); MVT::f64, FV, TV, LD), 0);
Result = FP;
return; return;
} }
break; break;
@ -401,10 +404,10 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
Opc = Alpha::STT; Opc = Alpha::STT;
} else } else
assert(0 && "Unknown operand"); assert(0 && "Unknown operand");
Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i], Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
getI64Imm((i - 6) * 8), getI64Imm((i - 6) * 8),
CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64), CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
Chain); Chain), 0);
} }
for (int i = 0; i < std::min(6, count); ++i) { for (int i = 0; i < std::min(6, count); ++i) {
if (MVT::isInteger(TypeOperands[i])) { if (MVT::isInteger(TypeOperands[i])) {
@ -424,14 +427,14 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
SDOperand GOT = getGlobalBaseReg(); SDOperand GOT = getGlobalBaseReg();
Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag); Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
Chain = CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
Addr.getOperand(0), Chain, InFlag); Addr.getOperand(0), Chain, InFlag), 0);
} else { } else {
Select(Addr, Addr); Select(Addr, Addr);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag); Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
Chain, InFlag ); Chain, InFlag), 0);
} }
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);

142
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -186,7 +186,7 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDOperand TmpPR, TmpPR2; SDOperand TmpPR, TmpPR2;
SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8; SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15; SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
SDOperand Result; SDNode *Result;
// we'll need copies of F0 and F1 // we'll need copies of F0 and F1
SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64); SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
@ -196,21 +196,27 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
if(!isFP) { if(!isFP) {
// first, load the inputs into FP regs. // first, load the inputs into FP regs.
TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1); TmpF1 =
SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
Chain = TmpF1.getValue(1); Chain = TmpF1.getValue(1);
TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2); TmpF2 =
SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
Chain = TmpF2.getValue(1); Chain = TmpF2.getValue(1);
// next, convert the inputs to FP // next, convert the inputs to FP
if(isSigned) { if(isSigned) {
TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1); TmpF3 =
SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1); Chain = TmpF3.getValue(1);
TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2); TmpF4 =
SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1); Chain = TmpF4.getValue(1);
} else { // is unsigned } else { // is unsigned
TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1); TmpF3 =
SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1); Chain = TmpF3.getValue(1);
TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2); TmpF4 =
SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1); Chain = TmpF4.getValue(1);
} }
@ -223,11 +229,11 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
// we start by computing an approximate reciprocal (good to 9 bits?) // we start by computing an approximate reciprocal (good to 9 bits?)
// note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate) // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
if(isFP) if(isFP)
TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1, TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
TmpF3, TmpF4); TmpF3, TmpF4), 0);
else else
TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1, TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
TmpF3, TmpF4); TmpF3, TmpF4), 0);
TmpPR = TmpF5.getValue(1); TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2); Chain = TmpF5.getValue(2);
@ -235,24 +241,24 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDOperand minusB; SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b // copies of -input_b
minusB = CurDAG->getTargetNode(IA64::SUB, MVT::i64, minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2); CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
Chain = minusB.getValue(1); Chain = minusB.getValue(1);
} }
SDOperand TmpE0, TmpY1, TmpE1, TmpY2; SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
TmpE0 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
TmpF4, TmpF5, F1, TmpPR); TmpF4, TmpF5, F1, TmpPR), 0);
Chain = TmpE0.getValue(1); Chain = TmpE0.getValue(1);
TmpY1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
TmpF5, TmpE0, TmpF5, TmpPR); TmpF5, TmpE0, TmpF5, TmpPR), 0);
Chain = TmpY1.getValue(1); Chain = TmpY1.getValue(1);
TmpE1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
TmpE0, TmpE0, F0, TmpPR); TmpE0, TmpE0, F0, TmpPR), 0);
Chain = TmpE1.getValue(1); Chain = TmpE1.getValue(1);
TmpY2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
TmpY1, TmpE1, TmpY1, TmpPR); TmpY1, TmpE1, TmpY1, TmpPR), 0);
Chain = TmpY2.getValue(1); Chain = TmpY2.getValue(1);
if(isFP) { // if this is an FP divide, we finish up here and exit early if(isFP) { // if this is an FP divide, we finish up here and exit early
@ -261,42 +267,44 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDOperand TmpE2, TmpY3, TmpQ0, TmpR0; SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
TmpE2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
TmpE1, TmpE1, F0, TmpPR); TmpE1, TmpE1, F0, TmpPR), 0);
Chain = TmpE2.getValue(1); Chain = TmpE2.getValue(1);
TmpY3 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
TmpY2, TmpE2, TmpY2, TmpPR); TmpY2, TmpE2, TmpY2, TmpPR), 0);
Chain = TmpY3.getValue(1); Chain = TmpY3.getValue(1);
TmpQ0 = CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec! TmpQ0 =
Tmp1, TmpY3, F0, TmpPR); SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
Tmp1, TmpY3, F0, TmpPR), 0);
Chain = TmpQ0.getValue(1); Chain = TmpQ0.getValue(1);
TmpR0 = CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec! TmpR0 =
Tmp2, TmpQ0, Tmp1, TmpPR); SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
Tmp2, TmpQ0, Tmp1, TmpPR), 0);
Chain = TmpR0.getValue(1); Chain = TmpR0.getValue(1);
// we want Result to have the same target register as the frcpa, so // we want Result to have the same target register as the frcpa, so
// we two-address hack it. See the comment "for this to work..." on // we two-address hack it. See the comment "for this to work..." on
// page 48 of Intel application note #245415 // page 48 of Intel application note #245415
Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg! Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR); TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
Chain = Result.getValue(1); Chain = SDOperand(Result, 1);
return Result; // XXX: early exit! return SDOperand(Result, 0); // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do: } else { // this is *not* an FP divide, so there's a bit left to do:
SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ; SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
TmpQ2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
TmpF3, TmpY2, F0, TmpPR); TmpF3, TmpY2, F0, TmpPR), 0);
Chain = TmpQ2.getValue(1); Chain = TmpQ2.getValue(1);
TmpR2 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
TmpF4, TmpQ2, TmpF3, TmpPR); TmpF4, TmpQ2, TmpF3, TmpPR), 0);
Chain = TmpR2.getValue(1); Chain = TmpR2.getValue(1);
// we want TmpQ3 to have the same target register as the frcpa? maybe we // we want TmpQ3 to have the same target register as the frcpa? maybe we
// should two-address hack it. See the comment "for this to work..." on page // should two-address hack it. See the comment "for this to work..." on page
// 48 of Intel application note #245415 // 48 of Intel application note #245415
TmpQ3 = CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64, TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR); TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0);
Chain = TmpQ3.getValue(1); Chain = TmpQ3.getValue(1);
// STORY: without these two-address instructions (TCFMAS1 and TCFMADS0) // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
@ -304,27 +312,30 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
// arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0. // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
if(isSigned) if(isSigned)
TmpQ = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3); TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
MVT::f64, TmpQ3), 0);
else else
TmpQ = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::f64, TmpQ3); TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
MVT::f64, TmpQ3), 0);
Chain = TmpQ.getValue(1); Chain = TmpQ.getValue(1);
if(isModulus) { if(isModulus) {
SDOperand FPminusB = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, SDOperand FPminusB =
minusB); SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
Chain = FPminusB.getValue(1); Chain = FPminusB.getValue(1);
SDOperand Remainder = CurDAG->getTargetNode(IA64::XMAL, MVT::f64, SDOperand Remainder =
TmpQ, FPminusB, TmpF1); SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
TmpQ, FPminusB, TmpF1), 0);
Chain = Remainder.getValue(1); Chain = Remainder.getValue(1);
Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder); Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
Chain = Result.getValue(1); Chain = SDOperand(Result, 1);
} else { // just an integer divide } else { // just an integer divide
Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ); Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
Chain = Result.getValue(1); Chain = SDOperand(Result, 1);
} }
return Result; return SDOperand(Result, 0);
} // wasn't an FP divide } // wasn't an FP divide
} }
@ -380,14 +391,15 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
// load the branch target's entry point [mem] and // load the branch target's entry point [mem] and
// GP value [mem+8] // GP value [mem+8]
SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64, SDOperand targetEntryPoint=
FnDescriptor); SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
Chain = targetEntryPoint.getValue(1); Chain = targetEntryPoint.getValue(1);
SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64, SDOperand targetGPAddr=
FnDescriptor, CurDAG->getConstant(8, MVT::i64)); SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
Chain = targetGPAddr.getValue(1); Chain = targetGPAddr.getValue(1);
SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64, SDOperand targetGP=
targetGPAddr); SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
Chain = targetGP.getValue(1); Chain = targetGP.getValue(1);
Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag); Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
@ -401,9 +413,11 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
// Finally, once everything is setup, emit the call itself // Finally, once everything is setup, emit the call itself
if(InFlag.Val) if(InFlag.Val)
Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, InFlag); Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
CallOperand, InFlag), 0);
else // there might be no arguments else // there might be no arguments
Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain); Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
CallOperand, Chain), 0);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
std::vector<SDOperand> CallResults; std::vector<SDOperand> CallResults;
@ -420,7 +434,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
case IA64ISD::GETFD: { case IA64ISD::GETFD: {
SDOperand Input; SDOperand Input;
Select(Input, N->getOperand(0)); Select(Input, N->getOperand(0));
Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input); Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
CodeGenMap[Op] = Result; CodeGenMap[Op] = Result;
return; return;
} }
@ -451,8 +465,8 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64)); CurDAG->getTargetFrameIndex(FI, MVT::i64));
else else
Result = CodeGenMap[Op] = CurDAG->getTargetNode(IA64::MOV, MVT::i64, Result = CodeGenMap[Op] = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64)); CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
return; return;
} }
@ -462,17 +476,17 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Constant *C = CP->get(); Constant *C = CP->get();
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64, SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment()); CP->getAlignment());
Result = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
CurDAG->getRegister(IA64::r1, MVT::i64), CPI); CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
return; return;
} }
case ISD::GlobalAddress: { case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal(); GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64); SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
CurDAG->getRegister(IA64::r1, MVT::i64), GA); CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
Result = CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp); Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
return; return;
} }
@ -501,7 +515,7 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Opc = IA64::LD1; // first we load a byte, then compare for != 0 Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit! if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
CurDAG->getTargetNode(Opc, MVT::i64, Address), SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
CurDAG->getRegister(IA64::r0, MVT::i64), CurDAG->getRegister(IA64::r0, MVT::i64),
Chain).getValue(Op.ResNo); Chain).getValue(Op.ResNo);
return; return;

147
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -368,17 +368,15 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) { N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
SDOperand Tmp; SDOperand Tmp;
Select(Tmp, N->getOperand(0).getOperand(0)); Select(Tmp, N->getOperand(0).getOperand(0));
Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Tmp, return CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Tmp,
getI32Imm(SH), getI32Imm(0), getI32Imm(31)); getI32Imm(SH), getI32Imm(0), getI32Imm(31));
return Op0.Val;
} }
SDOperand Tmp1, Tmp2; SDOperand Tmp1, Tmp2;
Select(Tmp1, ((Op0IsAND && fullMask) ? Op0.getOperand(0) : Op0)); Select(Tmp1, ((Op0IsAND && fullMask) ? Op0.getOperand(0) : Op0));
Select(Tmp2, (IsAndWithShiftOp ? Op1.getOperand(0).getOperand(0) Select(Tmp2, (IsAndWithShiftOp ? Op1.getOperand(0).getOperand(0)
: Op1.getOperand(0))); : Op1.getOperand(0)));
Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
return Op0.Val;
} }
return 0; return 0;
} }
@ -467,17 +465,17 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
unsigned Imm; unsigned Imm;
if (isIntImmediate(RHS, Imm) && if (isIntImmediate(RHS, Imm) &&
((U && isUInt16(Imm)) || (!U && isInt16(Imm)))) ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32, return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI,
LHS, getI32Imm(Imm & 0xFFFF)); MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0);
Select(RHS, RHS); Select(RHS, RHS);
return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32, return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
LHS, RHS); LHS, RHS), 0);
} else if (LHS.getValueType() == MVT::f32) { } else if (LHS.getValueType() == MVT::f32) {
Select(RHS, RHS); Select(RHS, RHS);
return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS); return SDOperand(CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS), 0);
} else { } else {
Select(RHS, RHS); Select(RHS, RHS);
return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS); return SDOperand(CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS), 0);
} }
} }
@ -552,7 +550,8 @@ SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
} }
std::vector<SDOperand> Result; std::vector<SDOperand> Result;
SDOperand CarryFromLo, Tmp; SDOperand Tmp;
SDNode *CarryFromLo;
if (isIntImmediate(N->getOperand(2), Imm) && if (isIntImmediate(N->getOperand(2), Imm) &&
((signed)Imm >= -32768 || (signed)Imm < 32768)) { ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
// Codegen the low 32 bits of the add. Interestingly, there is no // Codegen the low 32 bits of the add. Interestingly, there is no
@ -564,21 +563,22 @@ SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag, CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
LHSL, Tmp); LHSL, Tmp);
} }
CarryFromLo = CarryFromLo.getValue(1);
// Codegen the high 32 bits, adding zero, minus one, or the full value // Codegen the high 32 bits, adding zero, minus one, or the full value
// along with the carry flag produced by addc/addic. // along with the carry flag produced by addc/addic.
SDOperand ResultHi; SDOperand ResultHi;
if (ZE) if (ZE)
ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo); ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH,
SDOperand(CarryFromLo, 1)), 0);
else if (ME) else if (ME)
ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo); ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH,
SDOperand(CarryFromLo, 1)), 0);
else { else {
Select(Tmp, N->getOperand(3)); Select(Tmp, N->getOperand(3));
ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH, ResultHi = SDOperand(CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
Tmp, CarryFromLo); Tmp, SDOperand(CarryFromLo, 1)), 0);
} }
Result.push_back(CarryFromLo.getValue(0)); Result.push_back(SDOperand(CarryFromLo, 0));
Result.push_back(ResultHi); Result.push_back(ResultHi);
CodeGenMap[Op.getValue(0)] = Result[0]; CodeGenMap[Op.getValue(0)] = Result[0];
@ -594,10 +594,11 @@ SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
Select(RHSH, N->getOperand(3)); Select(RHSH, N->getOperand(3));
std::vector<SDOperand> Result; std::vector<SDOperand> Result;
Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag, Result.push_back(SDOperand(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32,
RHSL, LHSL)); MVT::Flag, RHSL, LHSL), 0));
Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH, Result.push_back(SDOperand(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32,
Result[0].getValue(1))); RHSH, LHSH,
Result[0].getValue(1)), 0));
CodeGenMap[Op.getValue(0)] = Result[0]; CodeGenMap[Op.getValue(0)] = Result[0];
CodeGenMap[Op.getValue(1)] = Result[1]; CodeGenMap[Op.getValue(1)] = Result[1];
return Result[Op.ResNo]; return Result[Op.ResNo];
@ -617,12 +618,13 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
switch (CC) { switch (CC) {
default: break; default: break;
case ISD::SETEQ: case ISD::SETEQ:
Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op); Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27), return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
getI32Imm(5), getI32Imm(31)); getI32Imm(5), getI32Imm(31));
case ISD::SETNE: { case ISD::SETNE: {
SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, SDOperand AD =
Op, getI32Imm(~0U)); SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U)), 0);
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1)); AD.getValue(1));
} }
@ -630,8 +632,9 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1), return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
getI32Imm(31), getI32Imm(31)); getI32Imm(31), getI32Imm(31));
case ISD::SETGT: { case ISD::SETGT: {
SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op); SDOperand T =
T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);; SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1), return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
getI32Imm(31), getI32Imm(31)); getI32Imm(31), getI32Imm(31));
} }
@ -642,29 +645,31 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
switch (CC) { switch (CC) {
default: break; default: break;
case ISD::SETEQ: case ISD::SETEQ:
Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(1)); Op, getI32Imm(1)), 0);
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
CurDAG->getTargetNode(PPC::LI, MVT::i32, SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
getI32Imm(0)), getI32Imm(0)), 0),
Op.getValue(1)); Op.getValue(1));
case ISD::SETNE: { case ISD::SETNE: {
Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op); Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U)); Op, getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), Op,
AD.getValue(1)); SDOperand(AD, 1));
} }
case ISD::SETLT: { case ISD::SETLT: {
SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
getI32Imm(1)); getI32Imm(1)), 0);
SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op); SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
Op), 0);
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1), return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
getI32Imm(31), getI32Imm(31)); getI32Imm(31), getI32Imm(31));
} }
case ISD::SETGT: case ISD::SETGT:
Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1), Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op,
getI32Imm(31), getI32Imm(31)); getI32Imm(1), getI32Imm(31),
getI32Imm(31)), 0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
} }
} }
@ -683,9 +688,10 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
InFlag).getValue(1); InFlag).getValue(1);
if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor()) if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg); IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
CCReg), 0);
else else
IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg); IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
if (!Inv) { if (!Inv) {
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR, return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
@ -693,9 +699,9 @@ SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
getI32Imm(31), getI32Imm(31)); getI32Imm(31), getI32Imm(31));
} else { } else {
SDOperand Tmp = SDOperand Tmp =
CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR, SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
getI32Imm((32-(3-Idx)) & 31), getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31),getI32Imm(31)); getI32Imm(31),getI32Imm(31)), 0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
} }
} }
@ -733,7 +739,8 @@ SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
// Copy the callee address into the CTR register. // Copy the callee address into the CTR register.
SDOperand Callee; SDOperand Callee;
Select(Callee, N->getOperand(1)); Select(Callee, N->getOperand(1));
Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain); Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee,
Chain), 0);
// Copy the callee address into R12 on darwin. // Copy the callee address into R12 on darwin.
SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32); SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
@ -783,8 +790,8 @@ SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
CallOperands.push_back(InFlag); // Strong dep on register copies. CallOperands.push_back(InFlag); // Strong dep on register copies.
else else
CallOperands.push_back(Chain); // Weak dep on whatever occurs before CallOperands.push_back(Chain); // Weak dep on whatever occurs before
Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
CallOperands); CallOperands), 0);
std::vector<SDOperand> CallResults; std::vector<SDOperand> CallResults;
@ -864,9 +871,9 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
return; return;
} }
Result = CodeGenMap[Op] = Result = CodeGenMap[Op] =
CurDAG->getTargetNode(PPC::ADDI, MVT::i32, SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
CurDAG->getTargetFrameIndex(FI, MVT::i32), CurDAG->getTargetFrameIndex(FI, MVT::i32),
getI32Imm(0)); getI32Imm(0)), 0);
return; return;
} }
case ISD::SDIV: { case ISD::SDIV: {
@ -880,18 +887,19 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDOperand N0; SDOperand N0;
Select(N0, N->getOperand(0)); Select(N0, N->getOperand(0));
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDOperand Op = SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(Imm))); N0, getI32Imm(Log2_32(Imm)));
Result = CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, Result = CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
Op.getValue(0), Op.getValue(1)); SDOperand(Op, 0), SDOperand(Op, 1));
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
SDOperand Op = SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(-Imm))); N0, getI32Imm(Log2_32(-Imm)));
SDOperand PT = SDOperand PT =
CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0), SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
Op.getValue(1)); SDOperand(Op, 0), SDOperand(Op, 1)),
0);
Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
} }
return; return;
@ -935,9 +943,10 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDOperand Tmp1, Tmp2; SDOperand Tmp1, Tmp2;
Select(Tmp1, N->getOperand(0).getOperand(0)); Select(Tmp1, N->getOperand(0).getOperand(0));
Select(Tmp2, N->getOperand(0).getOperand(1)); Select(Tmp2, N->getOperand(0).getOperand(1));
Result = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, Result = SDOperand(CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32,
getI32Imm(0), getI32Imm(MB), Tmp1, Tmp2,
getI32Imm(ME)); getI32Imm(0), getI32Imm(MB),
getI32Imm(ME)), 0);
return; return;
} }
} }
@ -994,11 +1003,12 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
N2C->getValue() == 1ULL && CC == ISD::SETNE) { N2C->getValue() == 1ULL && CC == ISD::SETNE) {
SDOperand LHS; SDOperand LHS;
Select(LHS, N->getOperand(0)); Select(LHS, N->getOperand(0));
SDOperand Tmp = SDNode *Tmp =
CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
LHS, getI32Imm(~0U)); LHS, getI32Imm(~0U));
Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS, Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
Tmp.getValue(1)); SDOperand(Tmp, 0), LHS,
SDOperand(Tmp, 1));
return; return;
} }
@ -1048,10 +1058,11 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
} }
unsigned Opc = getBCCForSetCC(CC); unsigned Opc = getBCCForSetCC(CC);
SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other, SDOperand CB =
CondCode, getI32Imm(Opc), SDOperand(CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
CondTrueBlock, CondFalseBlock, CondCode, getI32Imm(Opc),
Chain); CondTrueBlock, CondFalseBlock,
Chain), 0);
Result = CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB); Result = CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
} else { } else {
// Iterate to the next basic block // Iterate to the next basic block

53
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -1052,9 +1052,9 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
} }
Result = CodeGenMap[Op] = Result = CodeGenMap[Op] =
CurDAG->getTargetNode(SP::ADDri, MVT::i32, SDOperand(CurDAG->getTargetNode(SP::ADDri, MVT::i32,
CurDAG->getTargetFrameIndex(FI, MVT::i32), CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32)); CurDAG->getTargetConstant(0, MVT::i32)), 0);
return; return;
} }
case ISD::ADD_PARTS: { case ISD::ADD_PARTS: {
@ -1064,10 +1064,12 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Select(RHSL, N->getOperand(2)); Select(RHSL, N->getOperand(2));
Select(RHSH, N->getOperand(3)); Select(RHSH, N->getOperand(3));
// FIXME, handle immediate RHS. // FIXME, handle immediate RHS.
SDOperand Low = CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag, SDOperand Low =
LHSL, RHSL); SDOperand(CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
SDOperand Hi = CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH, LHSL, RHSL), 0);
Low.getValue(1)); SDOperand Hi =
SDOperand(CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH,
Low.getValue(1)), 0);
CodeGenMap[SDOperand(N, 0)] = Low; CodeGenMap[SDOperand(N, 0)] = Low;
CodeGenMap[SDOperand(N, 1)] = Hi; CodeGenMap[SDOperand(N, 1)] = Hi;
Result = Op.ResNo ? Hi : Low; Result = Op.ResNo ? Hi : Low;
@ -1079,10 +1081,12 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Select(LHSH, N->getOperand(1)); Select(LHSH, N->getOperand(1));
Select(RHSL, N->getOperand(2)); Select(RHSL, N->getOperand(2));
Select(RHSH, N->getOperand(3)); Select(RHSH, N->getOperand(3));
SDOperand Low = CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag, SDOperand Low =
LHSL, RHSL); SDOperand(CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
SDOperand Hi = CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, LHSL, RHSL), 0);
Low.getValue(1)); SDOperand Hi =
SDOperand(CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH,
Low.getValue(1)), 0);
CodeGenMap[SDOperand(N, 0)] = Low; CodeGenMap[SDOperand(N, 0)] = Low;
CodeGenMap[SDOperand(N, 1)] = Hi; CodeGenMap[SDOperand(N, 1)] = Hi;
Result = Op.ResNo ? Hi : Low; Result = Op.ResNo ? Hi : Low;
@ -1098,13 +1102,13 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
// Set the Y register to the high-part. // Set the Y register to the high-part.
SDOperand TopPart; SDOperand TopPart;
if (N->getOpcode() == ISD::SDIV) { if (N->getOpcode() == ISD::SDIV) {
TopPart = CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
CurDAG->getTargetConstant(31, MVT::i32)); CurDAG->getTargetConstant(31, MVT::i32)), 0);
} else { } else {
TopPart = CurDAG->getRegister(SP::G0, MVT::i32); TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
} }
TopPart = CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
CurDAG->getRegister(SP::G0, MVT::i32)); CurDAG->getRegister(SP::G0, MVT::i32)), 0);
// FIXME: Handle div by immediate. // FIXME: Handle div by immediate.
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
@ -1118,10 +1122,10 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Select(MulLHS, N->getOperand(0)); Select(MulLHS, N->getOperand(0));
Select(MulRHS, N->getOperand(1)); Select(MulRHS, N->getOperand(1));
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS); MulLHS, MulRHS);
// The high part is in the Y register. // The high part is in the Y register.
Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, Mul.getValue(1)); Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
return; return;
} }
case SPISD::CALL: case SPISD::CALL:
@ -1136,17 +1140,18 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDOperand Chain = N->getOperand(0); SDOperand Chain = N->getOperand(0);
SDOperand Tmp0 = N1; SDOperand Tmp0 = N1;
Select(Chain, Chain); Select(Chain, Chain);
SDNode *ResNode;
if (N->getNumOperands() == 3) { if (N->getNumOperands() == 3) {
Select(InFlag, N->getOperand(2)); Select(InFlag, N->getOperand(2));
Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, ResNode = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0,
Chain, InFlag); Chain, InFlag);
} else { } else {
Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, ResNode = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0,
Chain); Chain);
} }
Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); Chain = CodeGenMap[SDOperand(N, 0)] = SDOperand(ResNode, 0);
CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); CodeGenMap[SDOperand(N, 1)] = SDOperand(ResNode, 1);
Result = Result.getValue(Op.ResNo); Result = SDOperand(ResNode, Op.ResNo);
return; return;
} }
P47Fail:; P47Fail:;

36
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -521,12 +521,15 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
Select(Tmp1, Tmp1); Select(Tmp1, Tmp1);
Select(Tmp2, Tmp2); Select(Tmp2, Tmp2);
Select(Tmp3, Tmp3); Select(Tmp3, Tmp3);
Chain = CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1, SDNode *CNode =
Tmp2, Tmp3, Chain, InFlag); CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
InFlag = Chain.getValue(1); Tmp2, Tmp3, Chain, InFlag);
Chain = SDOperand(CNode, 0);
InFlag = SDOperand(CNode, 1);
} else { } else {
Select(N1, N1); Select(N1, N1);
InFlag = CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag); InFlag =
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
} }
Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag); Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
@ -601,12 +604,13 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
if (isSigned) { if (isSigned) {
// Sign extend the low part into the high part. // Sign extend the low part into the high part.
InFlag = CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag); InFlag =
SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
} else { } else {
// Zero out the high part, effectively zero extending the input. // Zero out the high part, effectively zero extending the input.
SDOperand ClrNode = SDOperand ClrNode =
CurDAG->getTargetNode(ClrOpcode, NVT, SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT,
CurDAG->getTargetConstant(0, NVT)); CurDAG->getTargetConstant(0, NVT)), 0);
Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT), Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
ClrNode, InFlag); ClrNode, InFlag);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
@ -617,12 +621,15 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
Select(Tmp1, Tmp1); Select(Tmp1, Tmp1);
Select(Tmp2, Tmp2); Select(Tmp2, Tmp2);
Select(Tmp3, Tmp3); Select(Tmp3, Tmp3);
Chain = CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1, SDNode *CNode =
Tmp2, Tmp3, Chain, InFlag); CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
InFlag = Chain.getValue(1); Tmp2, Tmp3, Chain, InFlag);
Chain = SDOperand(CNode, 0);
InFlag = SDOperand(CNode, 1);
} else { } else {
Select(N1, N1); Select(N1, N1);
InFlag = CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag); InFlag =
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
} }
Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg, Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
@ -645,7 +652,7 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
} }
SDOperand Tmp0, Tmp1; SDOperand Tmp0, Tmp1;
Select(Tmp0, Node->getOperand(0)); Select(Tmp0, Node->getOperand(0));
Select(Tmp1, CurDAG->getTargetNode(Opc, VT, Tmp0)); Select(Tmp1, SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0));
SDOperand InFlag = SDOperand(0,0); SDOperand InFlag = SDOperand(0,0);
Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Reg, Tmp1, InFlag); Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Reg, Tmp1, InFlag);
SDOperand Chain = Result.getValue(0); SDOperand Chain = Result.getValue(0);
@ -659,9 +666,10 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
Result = CurDAG->getCopyFromReg(Chain, Reg, VT, InFlag); Result = CurDAG->getCopyFromReg(Chain, Reg, VT, InFlag);
if (N.Val->hasOneUse()) if (N.Val->hasOneUse())
Result =CurDAG->SelectNodeTo(N.Val, Opc, VT, Result); Result = CurDAG->SelectNodeTo(N.Val, Opc, VT, Result);
else else
Result = CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result); Result = CodeGenMap[N] =
SDOperand(CurDAG->getTargetNode(Opc, VT, Result), 0);
return; return;
} }
} }