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Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75789 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Goodwin
2009-07-15 15:50:19 +00:00
parent 3af282f16a
commit 7ecc850cf1
1 changed files with 16 additions and 13 deletions
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25
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@@ -613,25 +613,23 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N, bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
SDValue &Base, SDValue &OffImm) { SDValue &Base, SDValue &OffImm) {
if (N.getOpcode() == ISD::ADD) { if ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::SUB)) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getZExtValue(); int RHSC = (int)RHS->getSExtValue();
if (RHSC < 0 && RHSC > -0x100) { // 8 bits. if (N.getOpcode() == ISD::SUB)
RHSC = -RHSC;
if ((RHSC >= -255) && (RHSC <= 255)) { // sign + 8 bits.
Base = N.getOperand(0); Base = N.getOperand(0);
OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true; return true;
} }
}
} else if (N.getOpcode() == ISD::SUB) { } else if (N.getOpcode() == ISD::SUB) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { Base = N;
int RHSC = (int)RHS->getZExtValue(); OffImm = CurDAG->getTargetConstant(0, MVT::i32);
if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
Base = N.getOperand(0);
OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
return true; return true;
} }
} }
}
return false; return false;
} }
@@ -700,6 +698,10 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
return true; return true;
} }
// Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
if (N.getOpcode() != ISD::ADD)
return false;
// Look for (R + R) or (R + (R << [1,2,3])). // Look for (R + R) or (R + (R << [1,2,3])).
unsigned ShAmt = 0; unsigned ShAmt = 0;
Base = N.getOperand(0); Base = N.getOperand(0);
@@ -727,9 +729,10 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
ShOpcVal = ARM_AM::no_shift; ShOpcVal = ARM_AM::no_shift;
} }
} else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) || } else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) ||
SelectT2AddrModeImm8 (Op, N, Base, ShImm)) SelectT2AddrModeImm8 (Op, N, Base, ShImm)) {
// Don't match if it's possible to match to one of the r +/- imm cases. // Don't match if it's possible to match to one of the r +/- imm cases.
return false; return false;
}
ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32); ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);