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[mips] Add backend support for Mips32r[35] and Mips64r[35].

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Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: tomatabacu, llvm-commits, atanasyan

Differential Revision: http://reviews.llvm.org/D7381


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2015-02-18 16:24:50 +00:00
parent 31840a62af
commit 7eedd07d5e
62 changed files with 4892 additions and 115 deletions
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36
test/CodeGen/Mips/llvm-ir/shl.ll
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@@ -3,10 +3,16 @@
; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
; RUN: -check-prefix=32R1-R2
; RUN: -check-prefix=32R1-R5
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6
; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
; RUN: -check-prefix=32R6 -check-prefix=R2-R6
@@ -22,6 +28,12 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=64R6 -check-prefix=R2-R6
@@ -101,16 +113,16 @@ entry:
; M2: jr $ra
; M2: nop
; 32R1-R2: sllv $[[T0:[0-9]+]], $4, $7
; 32R1-R2: not $[[T1:[0-9]+]], $7
; 32R1-R2: srl $[[T2:[0-9]+]], $5, 1
; 32R1-R2: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; 32R1-R2: or $2, $[[T0]], $[[T3]]
; 32R1-R2: sllv $[[T4:[0-9]+]], $5, $7
; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32
; 32R1-R2: movn $2, $[[T4]], $[[T5]]
; 32R1-R2: jr $ra
; 32R1-R2: movn $3, $zero, $[[T5]]
; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7
; 32R1-R5: not $[[T1:[0-9]+]], $7
; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1
; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; 32R1-R5: or $2, $[[T0]], $[[T3]]
; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7
; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
; 32R1-R5: movn $2, $[[T4]], $[[T5]]
; 32R1-R5: jr $ra
; 32R1-R5: movn $3, $zero, $[[T5]]
; 32R6: sllv $[[T0:[0-9]+]], $4, $7
; 32R6: not $[[T1:[0-9]+]], $7