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ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270 again (because three is a magic number). This should now no longer seg fault after r183459. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183464 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer
parent
01021a8b93
commit
7f155d7d2b
@ -1679,6 +1679,370 @@ let SchedModel = SwiftModel in {
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// Not serializing.
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def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>;
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// 4.2.39 Advanced SIMD and VFP, Load Single Element
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def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDRD$", "VLDRS$")>;
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// 4.2.40 Advanced SIMD and VFP, Store Single Element
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def : InstRW<[SwiftWriteLM4Cy], (instregex "VSTRD$", "VSTRS$")>;
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// 4.2.41 Advanced SIMD and VFP, Load Multiple
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// 4.2.42 Advanced SIMD and VFP, Store Multiple
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// Resource requirement for permuting, just reserves the resources.
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foreach Num = 1-28 in {
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def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> {
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let Latency = 0;
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let NumMicroOps = Num;
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let ResourceCycles = [Num];
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}
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}
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// Pre RA pseudos - load/store to a Q register as a D register pair.
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def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDMQIA$", "VSTMQIA$")>;
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// Post RA not modelled accurately. We assume that register use of width 64
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// bit maps to a D register, 128 maps to a Q register. Not all different kinds
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// are accurately represented.
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def SwiftWriteVLDM : SchedWriteVariant<[
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// Load of one S register.
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SchedVar<SwiftLMAddr1Pred, [SwiftWriteLM4Cy]>,
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// Load of one D register.
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SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo]>,
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// Load of 3 S register.
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SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM13CyNo, SwiftWriteP01OneCycle,
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SwiftVLDMPerm3]>,
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// Load of a Q register (not neccessarily true). We should not be mapping to
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// 4 S registers, either.
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SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo,
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SwiftWriteLM4CyNo, SwiftWriteLM4CyNo]>,
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// Load of 5 S registers.
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SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM13CyNo, SwiftWriteLM14CyNo,
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SwiftWriteLM17CyNo, SwiftWriteP01OneCycle,
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SwiftVLDMPerm5]>,
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// Load of 3 D registers. (Must also be able to handle s register list -
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// though, not accurate)
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SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM10Cy, SwiftWriteLM14CyNo,
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SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
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SwiftWriteP01OneCycle, SwiftVLDMPerm5]>,
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// Load of 7 S registers.
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SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
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SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
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SwiftWriteLM21CyNo, SwiftWriteP01OneCycle,
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SwiftVLDMPerm7]>,
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// Load of two Q registers.
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SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM13Cy, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteP01OneCycle, SwiftVLDMPerm2]>,
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// Load of 9 S registers.
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SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
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SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
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SwiftVLDMPerm9]>,
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// Load of 5 D registers.
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SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM10Cy, SwiftWriteLM14Cy,
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SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
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SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
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SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
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SwiftWriteP01OneCycle, SwiftVLDMPerm5]>,
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// Inaccurate: reuse describtion from 9 S registers.
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SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
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SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
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SwiftVLDMPerm9]>,
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// Load of three Q registers.
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SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM11Cy, SwiftWriteLM11Cy,
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SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
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SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
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SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
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SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
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SwiftWriteP01OneCycle, SwiftVLDMPerm3]>,
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// Inaccurate: reuse describtion from 9 S registers.
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SchedVar<SwiftLMAddr13Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
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SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
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SwiftVLDMPerm9]>,
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// Load of 7 D registers inaccurate.
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SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM10Cy, SwiftWriteLM14Cy,
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SwiftWriteLM14Cy, SwiftWriteLM14CyNo,
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SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
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SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
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SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
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SwiftWriteP01OneCycle, SwiftVLDMPerm7]>,
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SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy,
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SwiftWriteLM13Cy, SwiftWriteLM14Cy,
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SwiftWriteLM17Cy, SwiftWriteLM18CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
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SwiftVLDMPerm9]>,
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// Load of 4 Q registers.
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SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM7Cy, SwiftWriteLM10Cy,
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SwiftWriteLM11Cy, SwiftWriteLM14Cy,
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SwiftWriteLM15Cy, SwiftWriteLM18CyNo,
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SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
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SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
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SwiftWriteP01OneCycle, SwiftVLDMPerm4]>,
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// Unknow number of registers, just use resources for two registers.
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SchedVar<NoSchedPred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
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SwiftWriteLM13Cy, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
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SwiftWriteP01OneCycle, SwiftVLDMPerm2]>
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]> { let Variadic = 1; }
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def : InstRW<[SwiftWriteVLDM], (instregex "VLDM[SD](IA|DB)$")>;
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def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVLDM],
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(instregex "VLDM[SD](IA|DB)_UPD$")>;
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def SwiftWriteVSTM : SchedWriteVariant<[
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// One S register.
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SchedVar<SwiftLMAddr1Pred, [SwiftWriteSTM1]>,
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// One D register.
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SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM1]>,
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// Three S registers.
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SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM4]>,
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// Assume one Q register.
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SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM1]>,
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SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM6]>,
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// Assume three D registers.
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SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM4]>,
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SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM8]>,
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// Assume two Q registers.
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SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM3]>,
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SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM10]>,
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// Assume 5 D registers.
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SchedVar<SwiftLMAddr10Pred, [SwiftWriteSTM6]>,
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SchedVar<SwiftLMAddr11Pred, [SwiftWriteSTM12]>,
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// Asume three Q registers.
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SchedVar<SwiftLMAddr12Pred, [SwiftWriteSTM4]>,
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SchedVar<SwiftLMAddr13Pred, [SwiftWriteSTM14]>,
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// Assume 7 D registers.
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SchedVar<SwiftLMAddr14Pred, [SwiftWriteSTM8]>,
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SchedVar<SwiftLMAddr15Pred, [SwiftWriteSTM16]>,
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// Assume four Q registers.
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SchedVar<SwiftLMAddr16Pred, [SwiftWriteSTM5]>,
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// Asumme two Q registers.
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SchedVar<NoSchedPred, [SwiftWriteSTM3]>
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]> { let Variadic = 1; }
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def : InstRW<[SwiftWriteVSTM], (instregex "VSTM[SD](IA|DB)$")>;
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def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVSTM],
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(instregex "VSTM[SD](IA|DB)_UPD")>;
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// 4.2.43 Advanced SIMD, Element or Structure Load and Store
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def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
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let Latency = 4;
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let ResourceCycles = [2];
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}
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def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
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let Latency = 4;
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let ResourceCycles = [3];
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}
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foreach Num = 1-2 in {
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def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> {
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let Latency = 0;
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let NumMicroOps = Num;
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let ResourceCycles = [Num];
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}
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}
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// VLDx
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// Multiple structures.
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// Single element structure loads.
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// We assume aligned.
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// Single/two register.
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def : InstRW<[SwiftWriteLM4Cy], (instregex "VLD1(d|q)(8|16|32|64)$")>;
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def : InstRW<[SwiftWriteLM4Cy, SwiftWriteP01OneCycle],
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(instregex "VLD1(d|q)(8|16|32|64)wb")>;
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// Three register.
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def : InstRW<[SwiftWrite3xP2FourCy],
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(instregex "VLD1(d|q)(8|16|32|64)T$", "VLD1d64TPseudo")>;
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def : InstRW<[SwiftWrite3xP2FourCy, SwiftWriteP01OneCycle],
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(instregex "VLD1(d|q)(8|16|32|64)Twb")>;
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/// Four Register.
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def : InstRW<[SwiftWrite2xP2FourCy],
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(instregex "VLD1(d|q)(8|16|32|64)Q$", "VLD1d64QPseudo")>;
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def : InstRW<[SwiftWrite2xP2FourCy, SwiftWriteP01OneCycle],
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(instregex "VLD1(d|q)(8|16|32|64)Qwb")>;
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// Two element structure loads.
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// Two/four register.
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def : InstRW<[SwiftWriteLM9Cy, SwiftExt2xP0, SwiftVLDMPerm2],
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(instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>;
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def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
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SwiftVLDMPerm2],
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(instregex "VLD2(d|q|b)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB")>;
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// Three element structure.
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def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo,
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SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
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(instregex "VLD3(d|q)(8|16|32)$")>;
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def : InstRW<[SwiftWriteLM9Cy, SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
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(instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$")>;
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def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo,
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SwiftWriteP01OneCycle, SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
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(instregex "VLD3(d|q)(8|16|32)_UPD$")>;
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def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm3,
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SwiftWrite3xP2FourCy],
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(instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD")>;
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// Four element structure loads.
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def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy,
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SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4,
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SwiftWrite3xP2FourCy],
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(instregex "VLD4(d|q)(8|16|32)$")>;
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def : InstRW<[SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4,
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SwiftWrite3xP2FourCy],
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(instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$")>;
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def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy,
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SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
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SwiftVLDMPerm4, SwiftWrite3xP2FourCy],
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(instregex "VLD4(d|q)(8|16|32)_UPD")>;
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def : InstRW<[SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
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SwiftVLDMPerm4, SwiftWrite3xP2FourCy],
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(instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD")>;
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// Single all/lane loads.
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// One element structure.
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def : InstRW<[SwiftWriteLM6Cy, SwiftVLDMPerm2],
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(instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
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def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm2],
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(instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)",
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"VLD1LNq(8|16|32)Pseudo_UPD")>;
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// Two element structure.
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def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2],
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(instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$",
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"VLD2LN(d|q)(8|16|32)Pseudo$")>;
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def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftWriteP01OneCycle,
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SwiftExt1xP0, SwiftVLDMPerm2],
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(instregex "VLD2LN(d|q)(8|16|32)_UPD$")>;
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def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy,
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SwiftExt1xP0, SwiftVLDMPerm2],
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(instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb")>;
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def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy,
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SwiftExt1xP0, SwiftVLDMPerm2],
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(instregex "VLD2LN(d|q)(8|16|32)Pseudo_UPD")>;
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// Three element structure.
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def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftExt1xP0,
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SwiftVLDMPerm3],
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(instregex "VLD3(DUP|LN)(d|q)(8|16|32)$",
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"VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
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def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy,
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SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm3],
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(instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>;
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def : InstRW<[SwiftWriteLM7Cy, SwiftWriteP01OneCycle, SwiftWriteLM8Cy,
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SwiftWriteLM8Cy, SwiftExt1xP0, SwiftVLDMPerm3],
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(instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>;
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// Four element struture.
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def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo,
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SwiftWriteLM10CyNo, SwiftExt1xP0, SwiftVLDMPerm5],
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(instregex "VLD4(LN|DUP)(d|q)(8|16|32)$",
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"VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
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def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo,
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SwiftWriteLM10CyNo, SwiftWriteP01OneCycle, SwiftExt1xP0,
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SwiftVLDMPerm5],
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(instregex "VLD4(DUP|LN)(d|q)(8|16|32)_UPD")>;
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def : InstRW<[SwiftWriteLM8Cy, SwiftWriteP01OneCycle, SwiftWriteLM9Cy,
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SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftExt1xP0,
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SwiftVLDMPerm5],
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(instregex "VLD4(DUP|LN)(d|q)(8|16|32)Pseudo_UPD")>;
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// VSTx
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// Multiple structures.
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// Single element structure store.
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def : InstRW<[SwiftWrite1xP2], (instregex "VST1d(8|16|32|64)$")>;
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def : InstRW<[SwiftWrite2xP2], (instregex "VST1q(8|16|32|64)$")>;
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def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2],
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(instregex "VST1d(8|16|32|64)wb")>;
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def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2],
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(instregex "VST1q(8|16|32|64)wb")>;
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def : InstRW<[SwiftWrite3xP2],
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(instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$")>;
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def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite3xP2],
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(instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB")>;
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def : InstRW<[SwiftWrite4xP2],
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(instregex "VST1d(8|16|32|64)(Q|QPseudo)$")>;
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def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2],
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(instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)")>;
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// Two element structure store.
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def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1],
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(instregex "VST2(d|b)(8|16|32)$")>;
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def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1],
|
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(instregex "VST2(b|d)(8|16|32)wb")>;
|
||||
def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>;
|
||||
def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB")>;
|
||||
// Three element structure store.
|
||||
def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$")>;
|
||||
def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST3(d|q)(8|16|32)_UPD",
|
||||
"VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;
|
||||
// Four element structure store.
|
||||
def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$")>;
|
||||
def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm4],
|
||||
(instregex "VST4(d|q)(8|16|32)_UPD",
|
||||
"VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;
|
||||
// Single/all lane store.
|
||||
// One element structure.
|
||||
def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1],
|
||||
(instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>;
|
||||
def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1],
|
||||
(instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD")>;
|
||||
// Two element structure.
|
||||
def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>;
|
||||
def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST2LN(d|q)(8|16|32)_UPD",
|
||||
"VST2LN(d|q)(8|16|32)Pseudo_UPD")>;
|
||||
// Three element structure.
|
||||
def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>;
|
||||
def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST3LN(d|q)(8|16|32)_UPD",
|
||||
"VST3LN(d|q)(8|16|32)Pseudo_UPD")>;
|
||||
// Four element structure.
|
||||
def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$")>;
|
||||
def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2, SwiftVLDMPerm2],
|
||||
(instregex "VST4LN(d|q)(8|16|32)_UPD",
|
||||
"VST4LN(d|q)(8|16|32)Pseudo_UPD")>;
|
||||
|
||||
// Preload.
|
||||
def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
|
||||
let ResourceCycles = [0];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user