From 7f484a5fff140ade284a1af34641da067bea11ae Mon Sep 17 00:00:00 2001 From: Misha Brukman Date: Thu, 24 Jun 2004 23:51:00 +0000 Subject: [PATCH] * Lowercase the register names * Parenthesize assert() expressions correctly * Fix spacing around for() and if() statements git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14384 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPC32AsmPrinter.cpp | 22 +++++++++++----------- lib/Target/PowerPC/PPCAsmPrinter.cpp | 22 +++++++++++----------- lib/Target/PowerPC/PowerPCAsmPrinter.cpp | 22 +++++++++++----------- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/lib/Target/PowerPC/PPC32AsmPrinter.cpp b/lib/Target/PowerPC/PPC32AsmPrinter.cpp index 7c714ac7a82..ef605845b7f 100644 --- a/lib/Target/PowerPC/PPC32AsmPrinter.cpp +++ b/lib/Target/PowerPC/PPC32AsmPrinter.cpp @@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO, } // FALLTHROUGH case MachineOperand::MO_MachineRegister: - O << RI.get(MO.getReg()).Name; - return; + O << LowercaseString(RI.get(MO.getReg()).Name); + return; case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_UnextendedImmed: @@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask; unsigned int ArgType[5]; - ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; - ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; - ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; - ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; - ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; + ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; + ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; + ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; + ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; + ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; - assert((Desc.TSFlags & PPC32II::VMX == 0) && + assert(((Desc.TSFlags & PPC32II::VMX) == 0) && "Instruction requires VMX support"); - assert((Desc.TSFlags & PPC32II::PPC64 == 0) && + assert(((Desc.TSFlags & PPC32II::PPC64) == 0) && "Instruction requires 64 bit support"); //assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs"); ++EmittedInsts; @@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { printOp(MI->getOperand(2)); O << ")\n"; } else { - for(i = 0; i< ArgCount; i++) { + for (i = 0; i < ArgCount; ++i) { if (ArgType[i] == PPC32II::Gpr0 && MI->getOperand(i).getReg() == PPC32::R0) O << "0"; @@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { //std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n"; printOp(MI->getOperand(i)); } - if( ArgCount - 1 == i) + if (ArgCount - 1 == i) O << "\n"; else O << ", "; diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 7c714ac7a82..ef605845b7f 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO, } // FALLTHROUGH case MachineOperand::MO_MachineRegister: - O << RI.get(MO.getReg()).Name; - return; + O << LowercaseString(RI.get(MO.getReg()).Name); + return; case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_UnextendedImmed: @@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask; unsigned int ArgType[5]; - ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; - ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; - ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; - ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; - ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; + ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; + ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; + ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; + ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; + ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; - assert((Desc.TSFlags & PPC32II::VMX == 0) && + assert(((Desc.TSFlags & PPC32II::VMX) == 0) && "Instruction requires VMX support"); - assert((Desc.TSFlags & PPC32II::PPC64 == 0) && + assert(((Desc.TSFlags & PPC32II::PPC64) == 0) && "Instruction requires 64 bit support"); //assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs"); ++EmittedInsts; @@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { printOp(MI->getOperand(2)); O << ")\n"; } else { - for(i = 0; i< ArgCount; i++) { + for (i = 0; i < ArgCount; ++i) { if (ArgType[i] == PPC32II::Gpr0 && MI->getOperand(i).getReg() == PPC32::R0) O << "0"; @@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { //std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n"; printOp(MI->getOperand(i)); } - if( ArgCount - 1 == i) + if (ArgCount - 1 == i) O << "\n"; else O << ", "; diff --git a/lib/Target/PowerPC/PowerPCAsmPrinter.cpp b/lib/Target/PowerPC/PowerPCAsmPrinter.cpp index 7c714ac7a82..ef605845b7f 100644 --- a/lib/Target/PowerPC/PowerPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PowerPCAsmPrinter.cpp @@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO, } // FALLTHROUGH case MachineOperand::MO_MachineRegister: - O << RI.get(MO.getReg()).Name; - return; + O << LowercaseString(RI.get(MO.getReg()).Name); + return; case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_UnextendedImmed: @@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask; unsigned int ArgType[5]; - ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; - ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; - ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; - ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; - ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; + ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; + ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; + ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; + ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; + ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; - assert((Desc.TSFlags & PPC32II::VMX == 0) && + assert(((Desc.TSFlags & PPC32II::VMX) == 0) && "Instruction requires VMX support"); - assert((Desc.TSFlags & PPC32II::PPC64 == 0) && + assert(((Desc.TSFlags & PPC32II::PPC64) == 0) && "Instruction requires 64 bit support"); //assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs"); ++EmittedInsts; @@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { printOp(MI->getOperand(2)); O << ")\n"; } else { - for(i = 0; i< ArgCount; i++) { + for (i = 0; i < ArgCount; ++i) { if (ArgType[i] == PPC32II::Gpr0 && MI->getOperand(i).getReg() == PPC32::R0) O << "0"; @@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) { //std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n"; printOp(MI->getOperand(i)); } - if( ArgCount - 1 == i) + if (ArgCount - 1 == i) O << "\n"; else O << ", ";