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[X86][SSE] Improvements to byte shift shuffle matching
Since (v)pslldq / (v)psrldq instructions resolve to a single input argument it is useful to match it much earlier than we currently do - this prevents more complicated shuffles (notably insertion into a zero vector) matching before it. Differential Revision: http://reviews.llvm.org/D6409 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222796 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/X86
test/CodeGen/X86
@ -8217,6 +8217,11 @@ static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
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}
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// Try to use byte shift instructions.
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if (SDValue Shift = lowerVectorShuffleAsByteShift(
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DL, MVT::v2i64, V1, V2, Mask, DAG))
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return Shift;
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// If we have a single input from V2 insert that into V1 if we can do so
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// cheaply.
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if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
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@ -8243,11 +8248,6 @@ static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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Subtarget, DAG))
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return Blend;
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// Try to use byte shift instructions.
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if (SDValue Shift = lowerVectorShuffleAsByteShift(
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DL, MVT::v2i64, V1, V2, Mask, DAG))
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return Shift;
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// Try to use byte rotation instructions.
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// Its more profitable for pre-SSSE3 to use shuffles/unpacks.
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if (Subtarget->hasSSSE3())
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@ -8508,6 +8508,11 @@ static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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getV4X86ShuffleImm8ForMask(Mask, DAG));
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}
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// Try to use byte shift instructions.
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if (SDValue Shift = lowerVectorShuffleAsByteShift(
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DL, MVT::v4i32, V1, V2, Mask, DAG))
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return Shift;
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// There are special ways we can lower some single-element blends.
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if (NumV2Elements == 1)
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if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
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@ -8525,11 +8530,6 @@ static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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Subtarget, DAG))
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return Blend;
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// Try to use byte shift instructions.
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if (SDValue Shift = lowerVectorShuffleAsByteShift(
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DL, MVT::v4i32, V1, V2, Mask, DAG))
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return Shift;
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// Try to use byte rotation instructions.
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// Its more profitable for pre-SSSE3 to use shuffles/unpacks.
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if (Subtarget->hasSSSE3())
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@ -8593,17 +8593,17 @@ static SDValue lowerV8I16SingleInputVectorShuffle(
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Mask, Subtarget, DAG))
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return Broadcast;
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// Try to use byte shift instructions.
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if (SDValue Shift = lowerVectorShuffleAsByteShift(
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DL, MVT::v8i16, V, V, Mask, DAG))
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return Shift;
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
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if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
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// Try to use byte shift instructions.
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if (SDValue Shift = lowerVectorShuffleAsByteShift(
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DL, MVT::v8i16, V, V, Mask, DAG))
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return Shift;
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// Try to use byte rotation instructions.
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if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
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DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
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@ -9210,6 +9210,11 @@ static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
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"to be V1-input shuffles.");
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// Try to use byte shift instructions.
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if (SDValue Shift = lowerVectorShuffleAsByteShift(
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DL, MVT::v8i16, V1, V2, Mask, DAG))
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return Shift;
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// There are special ways we can lower some single-element blends.
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if (NumV2Inputs == 1)
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if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
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@ -9227,11 +9232,6 @@ static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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Subtarget, DAG))
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return Blend;
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// Try to use byte shift instructions.
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if (SDValue Shift = lowerVectorShuffleAsByteShift(
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DL, MVT::v8i16, V1, V2, Mask, DAG))
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return Shift;
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// Try to use byte rotation instructions.
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if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
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DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
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@ -271,9 +271,8 @@ define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) {
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define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test21:
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; CHECK: # BB#0:
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: movq %xmm0, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
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; CHECK-NEXT: retq
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%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
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@ -667,14 +667,12 @@ define <2 x i64> @shuffle_v2i64_0z(<2 x i64> %a) {
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define <2 x i64> @shuffle_v2i64_1z(<2 x i64> %a) {
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; SSE-LABEL: shuffle_v2i64_1z:
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; SSE: # BB#0:
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v2i64_1z:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
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; AVX-NEXT: retq
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%shuffle = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 3>
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ret <2 x i64> %shuffle
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@ -683,14 +681,12 @@ define <2 x i64> @shuffle_v2i64_1z(<2 x i64> %a) {
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define <2 x i64> @shuffle_v2i64_z0(<2 x i64> %a) {
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; SSE-LABEL: shuffle_v2i64_z0:
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; SSE: # BB#0:
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; SSE-NEXT: movq %xmm0, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v2i64_z0:
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; AVX: # BB#0:
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; AVX-NEXT: vmovq %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; AVX-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
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; AVX-NEXT: retq
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%shuffle = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> <i32 2, i32 0>
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ret <2 x i64> %shuffle
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@ -775,37 +775,27 @@ define <4 x i32> @shuffle_v4i32_zz4z(<4 x i32> %a) {
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define <4 x i32> @shuffle_v4i32_zuu4(<4 x i32> %a) {
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; SSE2-LABEL: shuffle_v4i32_zuu4:
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; SSE2: # BB#0:
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; SSE2-NEXT: xorps %xmm1, %xmm1
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; SSE2-NEXT: movss %xmm0, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,0]
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; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3]
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; SSE2-NEXT: retq
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;
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; SSE3-LABEL: shuffle_v4i32_zuu4:
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; SSE3: # BB#0:
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; SSE3-NEXT: xorps %xmm1, %xmm1
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; SSE3-NEXT: movss %xmm0, %xmm1
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; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,0]
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; SSE3-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3]
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; SSE3-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v4i32_zuu4:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: xorps %xmm1, %xmm1
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; SSSE3-NEXT: movss %xmm0, %xmm1
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,0]
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; SSSE3-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v4i32_zuu4:
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; SSE41: # BB#0:
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; SSE41-NEXT: xorps %xmm1, %xmm1
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; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,0]
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; SSE41-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4i32_zuu4:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,0]
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; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4>
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ret <4 x i32> %shuffle
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@ -1429,15 +1429,13 @@ define <8 x i16> @shuffle_v8i16_zzzzz8zz(i16 %i) {
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define <8 x i16> @shuffle_v8i16_zuuzuuz8(i16 %i) {
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; SSE-LABEL: shuffle_v8i16_zuuzuuz8:
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; SSE: # BB#0:
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; SSE-NEXT: movzwl %di, %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: movd %edi, %xmm0
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; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v8i16_zuuzuuz8:
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; AVX: # BB#0:
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; AVX-NEXT: movzwl %di, %eax
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; AVX-NEXT: vmovd %eax, %xmm0
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; AVX-NEXT: vmovd %edi, %xmm0
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; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1]
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; AVX-NEXT: retq
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%a = insertelement <8 x i16> undef, i16 %i, i32 0
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