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Disable a broken optimization

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-01-15 19:15:46 +00:00
parent bf40c4bfe1
commit 7f9975a793
2 changed files with 4 additions and 2 deletions
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3
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@@ -445,7 +445,8 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
ObjSize = 8; ObjSize = 8;
// If we can store this directly into the outgoing slot, do so. We can // If we can store this directly into the outgoing slot, do so. We can
// do this when all ArgRegs are used and if the outgoing slot is aligned. // do this when all ArgRegs are used and if the outgoing slot is aligned.
if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { // FIXME: McGill/misr fails with this.
if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
ValToStore = Val; ValToStore = Val;
break; break;
} }

3
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@@ -445,7 +445,8 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
ObjSize = 8; ObjSize = 8;
// If we can store this directly into the outgoing slot, do so. We can // If we can store this directly into the outgoing slot, do so. We can
// do this when all ArgRegs are used and if the outgoing slot is aligned. // do this when all ArgRegs are used and if the outgoing slot is aligned.
if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { // FIXME: McGill/misr fails with this.
if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
ValToStore = Val; ValToStore = Val;
break; break;
} }