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Make sure findRepresentativeClass picks the widest super-register.

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We want the representative register class to contain the largest
super-registers available. This makes the function less sensitive to the
register class numbering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156220 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-05-04 22:53:28 +00:00
parent 41afb9da2c
commit 7fc4d9cbc5
1 changed files with 10 additions and 6 deletions

16
lib/CodeGen/SelectionDAG/TargetLowering.cpp

@ -719,18 +719,22 @@ TargetLowering::findRepresentativeClass(EVT VT) const {
return std::make_pair(RC, 0);
// Compute the set of all super-register classes.
// Include direct sub-classes of RC in case there are no super-registers.
BitVector SuperRegRC(TRI->getNumRegClasses());
for (SuperRegClassIterator RCI(RC, TRI, true); RCI.isValid(); ++RCI)
for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
SuperRegRC.setBitsInMask(RCI.getMask());
// Find the first legal register class in the set.
// Find the first legal register class with the largest spill size.
const TargetRegisterClass *BestRC = RC;
for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
if (isLegalRC(SuperRC))
return std::make_pair(SuperRC, 1);
// We want the largest possible spill size.
if (SuperRC->getSize() <= BestRC->getSize())
continue;
if (!isLegalRC(SuperRC))
continue;
BestRC = SuperRC;
}
llvm_unreachable("Inconsistent register class tables.");
return std::make_pair(BestRC, 1);
}
/// computeRegisterProperties - Once all of the register classes are added,