6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-04 05:17:07 +00:00
Code Issues Projects Releases Wiki Activity

R600: Fix miscompiles when BFE has multiple uses

Browse Source 
SimplifyDemandedBits would break the other uses of the operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219819 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-10-15 17:58:34 +00:00
parent ddcfe81459
commit 7fdd553b66
2 changed files with 32 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@@ -2170,14 +2170,17 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
BitsFrom, ShiftVal); BitsFrom, ShiftVal);
} }
if (BitsFrom.hasOneUse()) {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
!DCI.isBeforeLegalizeOps()); !DCI.isBeforeLegalizeOps());
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) || if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) { TLI.SimplifyDemandedBits(BitsFrom, Demanded,
KnownZero, KnownOne, TLO)) {
DCI.CommitTargetLoweringOpt(TLO); DCI.CommitTargetLoweringOpt(TLO);
} }
}
break; break;
} }

22
test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll
View File

@@ -552,3 +552,25 @@ define void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
store i32 %bfe_u32, i32 addrspace(1)* %out, align 4 store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; Make sure that SimplifyDemandedBits doesn't cause the and to be
; reduced to the bits demanded by the bfe.
; XXX: The operand to v_bfe_u32 could also just directly be the load register.
; FUNC-LABEL: {{^}}simplify_bfe_u32_multi_use_arg:
; SI: BUFFER_LOAD_DWORD [[ARG:v[0-9]+]]
; SI: V_AND_B32_e32 [[AND:v[0-9]+]], 63, [[ARG]]
; SI: V_BFE_U32 [[BFE:v[0-9]+]], [[AND]], 2, 2
; SI-DAG: BUFFER_STORE_DWORD [[AND]]
; SI-DAG: BUFFER_STORE_DWORD [[BFE]]
; SI: S_ENDPGM
define void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0,
i32 addrspace(1)* %out1,
i32 addrspace(1)* %in) nounwind {
%src = load i32 addrspace(1)* %in, align 4
%and = and i32 %src, 63
%bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %and, i32 2, i32 2) nounwind readnone
store i32 %bfe_u32, i32 addrspace(1)* %out0, align 4
store i32 %and, i32 addrspace(1)* %out1, align 4
ret void
}