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[asan-asm-instrumentation] Fixed memory accesses with rbp as a base or an index register.
Summary: Fixed memory accesses with rbp as a base or an index register. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5819 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220283 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Yuri Gorshenin
parent
d75e7ad0c8
commit
7ffc5bb51a
@ -27,6 +27,8 @@
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include <algorithm>
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#include <cassert>
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#include <vector>
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namespace llvm {
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namespace {
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@ -61,26 +63,60 @@ std::string FuncName(unsigned AccessSize, bool IsWrite) {
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class X86AddressSanitizer : public X86AsmInstrumentation {
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public:
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struct RegisterContext {
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private:
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enum RegOffset {
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REG_OFFSET_ADDRESS = 0,
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REG_OFFSET_SHADOW,
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REG_OFFSET_SCRATCH
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};
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public:
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RegisterContext(unsigned AddressReg, unsigned ShadowReg,
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unsigned ScratchReg)
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: AddressReg(AddressReg), ShadowReg(ShadowReg), ScratchReg(ScratchReg) {
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unsigned ScratchReg) {
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for (unsigned Reg : { AddressReg, ShadowReg, ScratchReg }) {
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BusyRegs.push_back(convReg(Reg, MVT::i64));
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}
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}
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unsigned addressReg(MVT::SimpleValueType VT) const {
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return getX86SubSuperRegister(AddressReg, VT);
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unsigned AddressReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_ADDRESS], VT);
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}
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unsigned shadowReg(MVT::SimpleValueType VT) const {
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return getX86SubSuperRegister(ShadowReg, VT);
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unsigned ShadowReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_SHADOW], VT);
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}
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unsigned scratchReg(MVT::SimpleValueType VT) const {
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return getX86SubSuperRegister(ScratchReg, VT);
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unsigned ScratchReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_SCRATCH], VT);
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}
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const unsigned AddressReg;
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const unsigned ShadowReg;
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const unsigned ScratchReg;
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void AddBusyReg(unsigned Reg) {
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if (Reg != X86::NoRegister)
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BusyRegs.push_back(convReg(Reg, MVT::i64));
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}
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void AddBusyRegs(const X86Operand &Op) {
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AddBusyReg(Op.getMemBaseReg());
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AddBusyReg(Op.getMemIndexReg());
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}
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unsigned ChooseFrameReg(MVT::SimpleValueType VT) const {
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static const unsigned Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
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X86::RCX, X86::RDX, X86::RDI,
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X86::RSI };
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for (unsigned Reg : Candidates) {
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if (!std::count(BusyRegs.begin(), BusyRegs.end(), Reg))
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return convReg(Reg, VT);
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}
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return X86::NoRegister;
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}
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private:
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unsigned convReg(unsigned Reg, MVT::SimpleValueType VT) const {
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return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, VT);
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}
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std::vector<unsigned> BusyRegs;
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};
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X86AddressSanitizer(const MCSubtargetInfo &STI)
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@ -191,6 +227,9 @@ void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
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IsSmallMemAccess(AccessSize)
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? X86::RBX
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: X86::NoRegister /* ScratchReg */);
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RegCtx.AddBusyReg(DstReg);
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RegCtx.AddBusyReg(SrcReg);
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RegCtx.AddBusyReg(CntReg);
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InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
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@ -297,16 +336,17 @@ void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
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}
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const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
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RegisterContext RegCtx(X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */,
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IsSmallMemAccess(AccessSize)
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? X86::RCX
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: X86::NoRegister /* ScratchReg */);
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for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
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assert(Operands[Ix]);
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MCParsedAsmOperand &Op = *Operands[Ix];
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if (Op.isMem()) {
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X86Operand &MemOp = static_cast<X86Operand &>(Op);
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RegisterContext RegCtx(
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X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */,
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IsSmallMemAccess(AccessSize) ? X86::RCX
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: X86::NoRegister /* ScratchReg */);
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RegCtx.AddBusyRegs(MemOp);
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InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
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InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out);
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InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
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@ -414,42 +454,51 @@ public:
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virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) override {
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
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assert(LocalFrameReg != X86::NoRegister);
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const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (MRI && FrameReg != X86::NoRegister) {
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SpillReg(Out, X86::EBP);
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SpillReg(Out, LocalFrameReg);
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if (FrameReg == X86::ESP) {
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Out.EmitCFIAdjustCfaOffset(4 /* byte size of the FrameReg */);
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Out.EmitCFIRelOffset(MRI->getDwarfRegNum(X86::EBP, true /* IsEH */), 0);
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Out.EmitCFIAdjustCfaOffset(4 /* byte size of the LocalFrameReg */);
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Out.EmitCFIRelOffset(
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MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EBP).addReg(FrameReg));
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Out,
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MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg));
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Out.EmitCFIRememberState();
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Out.EmitCFIDefCfaRegister(MRI->getDwarfRegNum(X86::EBP, true /* IsEH */));
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Out.EmitCFIDefCfaRegister(
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MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
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}
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SpillReg(Out, RegCtx.addressReg(MVT::i32));
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SpillReg(Out, RegCtx.shadowReg(MVT::i32));
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if (RegCtx.ScratchReg != X86::NoRegister)
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SpillReg(Out, RegCtx.scratchReg(MVT::i32));
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SpillReg(Out, RegCtx.AddressReg(MVT::i32));
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SpillReg(Out, RegCtx.ShadowReg(MVT::i32));
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if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
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SpillReg(Out, RegCtx.ScratchReg(MVT::i32));
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StoreFlags(Out);
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}
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virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) override {
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
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assert(LocalFrameReg != X86::NoRegister);
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RestoreFlags(Out);
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if (RegCtx.ScratchReg != X86::NoRegister)
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RestoreReg(Out, RegCtx.scratchReg(MVT::i32));
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RestoreReg(Out, RegCtx.shadowReg(MVT::i32));
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RestoreReg(Out, RegCtx.addressReg(MVT::i32));
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if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
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RestoreReg(Out, RegCtx.ScratchReg(MVT::i32));
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RestoreReg(Out, RegCtx.ShadowReg(MVT::i32));
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RestoreReg(Out, RegCtx.AddressReg(MVT::i32));
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
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RestoreReg(Out, X86::EBP);
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RestoreReg(Out, LocalFrameReg);
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Out.EmitCFIRestoreState();
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if (FrameReg == X86::ESP)
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Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the FrameReg */);
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Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the LocalFrameReg */);
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}
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}
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@ -477,7 +526,7 @@ private:
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.addReg(X86::ESP)
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.addImm(-16));
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.addressReg(MVT::i32)));
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Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(MVT::i32)));
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const std::string &Fn = FuncName(AccessSize, IsWrite);
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MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
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@ -490,12 +539,12 @@ private:
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void X86AddressSanitizer32::InstrumentMemOperandSmall(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
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unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
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unsigned ShadowRegI8 = RegCtx.shadowReg(MVT::i8);
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unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
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unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
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assert(RegCtx.ScratchReg != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.scratchReg(MVT::i32);
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assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
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ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
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@ -565,8 +614,8 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
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void X86AddressSanitizer32::InstrumentMemOperandLarge(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
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unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
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unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
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ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
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@ -663,44 +712,53 @@ public:
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virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) override {
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
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assert(LocalFrameReg != X86::NoRegister);
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const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (MRI && FrameReg != X86::NoRegister) {
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SpillReg(Out, X86::RBP);
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if (FrameReg == X86::RSP) {
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Out.EmitCFIAdjustCfaOffset(8 /* byte size of the FrameReg */);
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Out.EmitCFIRelOffset(MRI->getDwarfRegNum(X86::RBP, true /* IsEH */), 0);
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Out.EmitCFIAdjustCfaOffset(8 /* byte size of the LocalFrameReg */);
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Out.EmitCFIRelOffset(
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MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RBP).addReg(FrameReg));
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Out,
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MCInstBuilder(X86::MOV64rr).addReg(LocalFrameReg).addReg(FrameReg));
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Out.EmitCFIRememberState();
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Out.EmitCFIDefCfaRegister(MRI->getDwarfRegNum(X86::RBP, true /* IsEH */));
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Out.EmitCFIDefCfaRegister(
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MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
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}
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EmitAdjustRSP(Ctx, Out, -128);
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SpillReg(Out, RegCtx.shadowReg(MVT::i64));
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SpillReg(Out, RegCtx.addressReg(MVT::i64));
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if (RegCtx.ScratchReg != X86::NoRegister)
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SpillReg(Out, RegCtx.scratchReg(MVT::i64));
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SpillReg(Out, RegCtx.ShadowReg(MVT::i64));
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SpillReg(Out, RegCtx.AddressReg(MVT::i64));
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if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
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SpillReg(Out, RegCtx.ScratchReg(MVT::i64));
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StoreFlags(Out);
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}
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virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) override {
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
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assert(LocalFrameReg != X86::NoRegister);
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RestoreFlags(Out);
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if (RegCtx.ScratchReg != X86::NoRegister)
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RestoreReg(Out, RegCtx.scratchReg(MVT::i64));
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RestoreReg(Out, RegCtx.addressReg(MVT::i64));
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RestoreReg(Out, RegCtx.shadowReg(MVT::i64));
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if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
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RestoreReg(Out, RegCtx.ScratchReg(MVT::i64));
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RestoreReg(Out, RegCtx.AddressReg(MVT::i64));
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RestoreReg(Out, RegCtx.ShadowReg(MVT::i64));
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EmitAdjustRSP(Ctx, Out, 128);
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
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RestoreReg(Out, X86::RBP);
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RestoreReg(Out, LocalFrameReg);
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Out.EmitCFIRestoreState();
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if (FrameReg == X86::RSP)
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Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the FrameReg */);
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Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the LocalFrameReg */);
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}
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}
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@ -736,9 +794,9 @@ private:
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.addReg(X86::RSP)
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.addImm(-16));
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if (RegCtx.AddressReg != X86::RDI) {
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if (RegCtx.AddressReg(MVT::i64) != X86::RDI) {
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EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg(
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RegCtx.addressReg(MVT::i64)));
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RegCtx.AddressReg(MVT::i64)));
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}
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const std::string &Fn = FuncName(AccessSize, IsWrite);
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MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
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@ -751,14 +809,14 @@ private:
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void X86AddressSanitizer64::InstrumentMemOperandSmall(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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unsigned AddressRegI64 = RegCtx.addressReg(MVT::i64);
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unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
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unsigned ShadowRegI64 = RegCtx.shadowReg(MVT::i64);
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unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
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unsigned ShadowRegI8 = RegCtx.shadowReg(MVT::i8);
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unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
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unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
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unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
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unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
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assert(RegCtx.ScratchReg != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.scratchReg(MVT::i32);
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assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
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ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
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@ -827,8 +885,8 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
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void X86AddressSanitizer64::InstrumentMemOperandLarge(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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unsigned AddressRegI64 = RegCtx.addressReg(MVT::i64);
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unsigned ShadowRegI64 = RegCtx.shadowReg(MVT::i64);
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unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
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unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
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ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
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@ -3,20 +3,20 @@
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# RUN: llvm-mc %s -triple=i386-unknown-linux-gnu -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
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# CHECK-LABEL: swap_cfa_rbp
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# CHECK: pushl %ebp
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# CHECK-LABEL: load4b_cfa_rbp
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# CHECK: pushl %ebx
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# CHECK-NOT: .cfi_adjust_cfa_offset 8
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# CHECK: movl %ebp, %ebp
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# CHECK: movl %ebp, %ebx
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# CHECK: .cfi_remember_state
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# CHECK: .cfi_def_cfa_register %ebp
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# CHECK: popl %ebp
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# CHECK: .cfi_def_cfa_register %ebx
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# CHECK: popl %ebx
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# CHECK: .cfi_restore_state
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# CHECK-NOT: .cfi_adjust_cfa_offset -8
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# CHECK: retl
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.text
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.globl swap_cfa_rbp
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.type swap_cfa_rbp,@function
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.globl load4b_cfa_rbp
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.type load4b_cfa_rbp,@function
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swap_cfa_rbp: # @swap_cfa_rbp
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.cfi_startproc
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pushl %ebp
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@ -25,34 +25,28 @@ swap_cfa_rbp: # @swap_cfa_rbp
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movl %esp, %ebp
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.cfi_def_cfa_register %ebp
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movl 8(%ebp), %eax
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movl 12(%ebp), %ecx
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movl (%ecx), %ecx
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movl %ecx, (%eax)
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popl %ebp
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retl
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.cfi_endproc
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# CHECK-LABEL: swap_cfa_rsp
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# CHECK: pushl %ebp
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# CHECK-LABEL: load4b_cfa_rsp
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# CHECK: pushl %ebx
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# CHECK: .cfi_adjust_cfa_offset 4
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# CHECK: movl %esp, %ebp
|
||||
# CHECK: movl %esp, %ebx
|
||||
# CHECK: .cfi_remember_state
|
||||
# CHECK: .cfi_def_cfa_register %ebp
|
||||
# CHECK: popl %ebp
|
||||
# CHECK: .cfi_def_cfa_register %ebx
|
||||
# CHECK: popl %ebx
|
||||
# CHECK: .cfi_restore_state
|
||||
# CHECK: retl
|
||||
|
||||
.globl swap_cfa_rsp
|
||||
.type swap_cfa_rsp,@function
|
||||
.globl load4b_cfa_rsp
|
||||
.type load4b_cfa_rsp,@function
|
||||
swap_cfa_rsp: # @swap_cfa_rsp
|
||||
.cfi_startproc
|
||||
pushl %ebp
|
||||
.cfi_offset %ebp, 0
|
||||
movl %esp, %ebp
|
||||
movl 8(%ebp), %eax
|
||||
movl 12(%ebp), %ecx
|
||||
movl (%ecx), %ecx
|
||||
movl %ecx, (%eax)
|
||||
popl %ebp
|
||||
retl
|
||||
.cfi_endproc
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user