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Make the verifier a little quieter on instructions that it's probably

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(and likely) wrong about anyhow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119320 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2010-11-16 01:58:21 +00:00
parent b8efa6b475
commit 800e57313e
1 changed files with 3 additions and 1 deletions
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4
lib/CodeGen/MachineVerifier.cpp
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@@ -558,7 +558,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
else if (MO->isImplicit()) else if (MO->isImplicit())
report("Explicit definition marked as implicit", MO, MONum); report("Explicit definition marked as implicit", MO, MONum);
} else if (MONum < TI.getNumOperands()) { } else if (MONum < TI.getNumOperands()) {
if (MO->isReg()) { // Don't check if it's a variadic instruction. See, e.g., LDM_RET in the arm
// back end.
if (MO->isReg() && MONum != TI.getNumOperands()-1) {
if (MO->isDef()) if (MO->isDef())
report("Explicit operand marked as def", MO, MONum); report("Explicit operand marked as def", MO, MONum);
if (MO->isImplicit()) if (MO->isImplicit())