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Can't fold loads into alias vector SSE ops used for scalar operation. The load

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address has to be 16-byte aligned but the values aren't spilled to 128-bit
locations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27732 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-04-16 06:58:19 +00:00
parent f3f69decca
commit 800f12df1e
1 changed files with 0 additions and 8 deletions
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8
lib/Target/X86/X86RegisterInfo.cpp
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@ -464,14 +464,6 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
return MakeRMInst(X86::Int_COMISSrm, FrameIndex, MI);
case X86::Int_COMISDrr:
return MakeRMInst(X86::Int_COMISDrm, FrameIndex, MI);
case X86::FsANDPSrr: return MakeRMInst(X86::FsANDPSrm, FrameIndex, MI);
case X86::FsANDPDrr: return MakeRMInst(X86::FsANDPDrm, FrameIndex, MI);
case X86::FsORPSrr: return MakeRMInst(X86::FsORPSrm, FrameIndex, MI);
case X86::FsORPDrr: return MakeRMInst(X86::FsORPDrm, FrameIndex, MI);
case X86::FsXORPSrr: return MakeRMInst(X86::FsXORPSrm, FrameIndex, MI);
case X86::FsXORPDrr: return MakeRMInst(X86::FsXORPDrm, FrameIndex, MI);
case X86::FsANDNPSrr: return MakeRMInst(X86::FsANDNPSrm, FrameIndex, MI);
case X86::FsANDNPDrr: return MakeRMInst(X86::FsANDNPDrm, FrameIndex, MI);
// Packed SSE instructions
case X86::MOVAPSrr: return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI);
case X86::MOVAPDrr: return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI);