6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

Thumb parsing and encoding for tSTRspi.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138348 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-23 18:39:41 +00:00
parent 4c821d800a
commit 803b1aa8ef
2 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMInstrThumb.td
View File

@ -194,6 +194,8 @@ def t_addrmode_is1 : Operand<i32>,
// t_addrmode_sp := sp + imm8 * 4
//
// FIXME: This really shouldn't have an explicit SP operand at all. It should
// be implicit, just like in the instruction encoding itself.
def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
def t_addrmode_sp : Operand<i32>,
ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {

8
test/MC/ARM/basic-thumb-instructions.s
View File

@ -444,11 +444,19 @@ _func:
str r2, [r7, #0]
str r5, [r1, #4]
str r3, [r7, #124]
str r2, [sp]
str r3, [sp, #0]
str r4, [sp, #20]
str r5, [sp, #1020]
@ CHECK: str r2, [r7] @ encoding: [0x3a,0x60]
@ CHECK: str r2, [r7] @ encoding: [0x3a,0x60]
@ CHECK: str r5, [r1, #4] @ encoding: [0x4d,0x60]
@ CHECK: str r3, [r7, #124] @ encoding: [0xfb,0x67]
@ CHECK: str r2, [sp] @ encoding: [0x00,0x92]
@ CHECK: str r3, [sp] @ encoding: [0x00,0x93]
@ CHECK: str r4, [sp, #20] @ encoding: [0x05,0x94]
@ CHECK: str r5, [sp, #1020] @ encoding: [0xff,0x95]
@------------------------------------------------------------------------------