6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

Do Materialize Floating Point in Mips Fast-Isel

Browse Source 
Summary:
Implement materialize of floating point literals in Mips Fast-Isel

Reopened version of D3659

Test Plan: simplestorefp1.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4071

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210546 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
2014-06-10 16:45:44 +00:00
parent c0edcf7de8
commit 805c9e4943
2 changed files with 61 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
lib/Target/Mips/MipsFastISel.cpp
View File

@@ -167,9 +167,14 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
//
// more cases will be handled here in following patches.
//
if (VT != MVT::i32)
if (VT == MVT::i32)
EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
else if (VT == MVT::f32)
EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset);
else if (VT == MVT::f64)
EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset);
else
return false;
EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
return true;
}
@@ -229,6 +234,22 @@ bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
}
unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
if (VT == MVT::f32) {
const TargetRegisterClass *RC = &Mips::FGR32RegClass;
unsigned DestReg = createResultReg(RC);
unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
return DestReg;
} else if (VT == MVT::f64) {
const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
unsigned DestReg = createResultReg(RC);
unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
unsigned TempReg2 =
Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
return DestReg;
}
return 0;
}