From 806fcc040e0bc7962891f12d6e09fc86f0bc2184 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 6 Jul 2011 21:33:38 +0000 Subject: [PATCH] Don't require pseudo-instructions to carry encoding information. For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/Target.td | 8 ++++++++ utils/TableGen/ARMDecoderEmitter.cpp | 3 +++ utils/TableGen/CodeEmitterGen.cpp | 9 ++++++--- utils/TableGen/CodeGenInstruction.cpp | 1 + utils/TableGen/CodeGenInstruction.h | 1 + utils/TableGen/EDEmitter.cpp | 5 +++++ utils/TableGen/FixedLenDecoderEmitter.cpp | 9 +++++---- 7 files changed, 29 insertions(+), 7 deletions(-) diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 4d7116b53b0..7f2cbe2ebc2 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -324,6 +324,9 @@ class Instruction { bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? + bit isPseudo = 0; // Is this instruction a pseudo-instruction? + // If so, won't have encoding information for + // the [MC]CodeEmitter stuff. // Side effect flags - When set, the flags have these meanings: // @@ -338,6 +341,11 @@ class Instruction { // Is this instruction a "real" instruction (with a distinct machine // encoding), or is it a pseudo instruction used for codegen modeling // purposes. + // FIXME: For now this is distinct from isPseudo, above, as code-gen-only + // instructions can (and often do) still have encoding information + // associated with them. Once we've migrated all of them over to true + // pseudo-instructions that are lowered to real instructions prior to + // the printer/emitter, we can remove this attribute and just use isPseudo. bit isCodeGenOnly = 0; // Is this instruction a pseudo instruction for use by the assembler parser. diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp index a7cbbcd84b7..8a5dc8ba154 100644 --- a/utils/TableGen/ARMDecoderEmitter.cpp +++ b/utils/TableGen/ARMDecoderEmitter.cpp @@ -421,6 +421,9 @@ public: protected: // Populates the insn given the uid. void insnWithID(insn_t &Insn, unsigned Opcode) const { + if (AllInstructions[Opcode]->isPseudo) + return; + BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); for (unsigned i = 0; i < BIT_WIDTH; ++i) diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index 9d4dc5c4607..d828dfc25db 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -34,7 +34,8 @@ void CodeEmitterGen::reverseBits(std::vector &Insts) { for (std::vector::iterator I = Insts.begin(), E = Insts.end(); I != E; ++I) { Record *R = *I; - if (R->getValueAsString("Namespace") == "TargetOpcode") + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) continue; BitsInit *BI = R->getValueAsBitsInit("Inst"); @@ -231,7 +232,8 @@ void CodeEmitterGen::run(raw_ostream &o) { const CodeGenInstruction *CGI = *IN; Record *R = CGI->TheDef; - if (R->getValueAsString("Namespace") == "TargetOpcode") { + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) { o << " 0U,\n"; continue; } @@ -255,7 +257,8 @@ void CodeEmitterGen::run(raw_ostream &o) { for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); IC != EC; ++IC) { Record *R = *IC; - if (R->getValueAsString("Namespace") == "TargetOpcode") + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) continue; const std::string &InstName = R->getValueAsString("Namespace") + "::" + R->getName(); diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index 5fa91be4885..28b56ba1295 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -311,6 +311,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R), Operands(R) { isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove"); hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq"); hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq"); + isPseudo = R->getValueAsBit("isPseudo"); ImplicitDefs = R->getValueAsListOfDefs("Defs"); ImplicitUses = R->getValueAsListOfDefs("Uses"); diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h index 5f1e0bea766..ad39722ab0f 100644 --- a/utils/TableGen/CodeGenInstruction.h +++ b/utils/TableGen/CodeGenInstruction.h @@ -235,6 +235,7 @@ namespace llvm { bool isAsCheapAsAMove; bool hasExtraSrcRegAllocReq; bool hasExtraDefRegAllocReq; + bool isPseudo; CodeGenInstruction(Record *R); diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index 4c0d385670d..9870d91f3ef 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -774,6 +774,11 @@ static void populateInstInfo(CompoundConstantEmitter &infoArray, for (index = 0; index < numInstructions; ++index) { const CodeGenInstruction& inst = *numberedInstructions[index]; + // We don't need to do anything for pseudo-instructions, as we'll never + // see them here. We'll only see real instructions. + if (inst.isPseudo) + continue; + CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter; infoArray.addEntry(infoStruct); diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp index ba6cd863c81..c9dcb01de00 100644 --- a/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -1225,14 +1225,14 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, // // This also removes pseudo instructions from considerations of disassembly, // which is a better design and less fragile than the name matchings. - BitsInit &Bits = getBitsField(Def, "Inst"); - if (Bits.allInComplete()) return false; - // Ignore "asm parser only" instructions. if (Def.getValueAsBit("isAsmParserOnly") || Def.getValueAsBit("isCodeGenOnly")) return false; + BitsInit &Bits = getBitsField(Def, "Inst"); + if (Bits.allInComplete()) return false; + std::vector InsnOperands; // If the instruction has specified a custom decoding hook, use that instead @@ -1354,7 +1354,8 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, void FixedLenDecoderEmitter::populateInstructions() { for (unsigned i = 0, e = NumberedInstructions.size(); i < e; ++i) { Record *R = NumberedInstructions[i]->TheDef; - if (R->getValueAsString("Namespace") == "TargetOpcode") + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) continue; if (populateInstruction(*NumberedInstructions[i], i))