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Suppress '(x < y) ? a : 0 -> (x < y) & a' transform on X86 architectures with dedicated mask registers.

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Patch by Aleksey Bader.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196386 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron McInally 2013-12-04 14:52:33 +00:00
parent 8467740001
commit 80955805e4
2 changed files with 19 additions and 7 deletions
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15
lib/Target/X86/X86ISelLowering.cpp
View File

@ -17010,12 +17010,13 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
// Simplify vector selection if the selector will be produced by CMPP*/PCMP*. // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC && if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
// Check if SETCC has already been promoted // Check if SETCC has already been promoted
TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) { TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
// Check that condition value type matches vselect operand type
CondVT == VT) {
assert(Cond.getValueType().isVector() && assert(Cond.getValueType().isVector() &&
"vector select expects a vector selector!"); "vector select expects a vector selector!");
EVT IntVT = Cond.getValueType();
bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode()); bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
@ -17030,7 +17031,7 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
ISD::CondCode NewCC = ISD::CondCode NewCC =
ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
Cond.getOperand(0).getValueType().isInteger()); Cond.getOperand(0).getValueType().isInteger());
Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC); Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
std::swap(LHS, RHS); std::swap(LHS, RHS);
TValIsAllOnes = FValIsAllOnes; TValIsAllOnes = FValIsAllOnes;
FValIsAllZeros = TValIsAllZeros; FValIsAllZeros = TValIsAllZeros;
@ -17043,11 +17044,11 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
if (TValIsAllOnes && FValIsAllZeros) if (TValIsAllOnes && FValIsAllZeros)
Ret = Cond; Ret = Cond;
else if (TValIsAllOnes) else if (TValIsAllOnes)
Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond, Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
DAG.getNode(ISD::BITCAST, DL, IntVT, RHS)); DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
else if (FValIsAllZeros) else if (FValIsAllZeros)
Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond, Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
DAG.getNode(ISD::BITCAST, DL, IntVT, LHS)); DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
return DAG.getNode(ISD::BITCAST, DL, VT, Ret); return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
} }

11
test/CodeGen/X86/avx512-vselect-crash.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; CHECK-LABEL: test
; CHECK: vmovdqu32
; CHECK: ret
define <16 x i32> @test() {
entry:
%0 = icmp slt <16 x i32> undef, undef
%1 = select <16 x i1> %0, <16 x i32> undef, <16 x i32> zeroinitializer
ret <16 x i32> %1
}