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Teach the X86 backend about non-i32 inline asm register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28139 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3998,14 +3998,34 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
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default: break; // Unknown constriant letter
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case 'r': // GENERAL_REGS
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case 'R': // LEGACY_REGS
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return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
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X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
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if (VT == MVT::i32)
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return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
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X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
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else if (VT == MVT::i16)
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return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
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X86::SI, X86::DI, X86::BP, X86::SP, 0);
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else if (VT == MVT::i8)
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return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
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break;
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case 'l': // INDEX_REGS
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return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
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X86::ESI, X86::EDI, X86::EBP, 0);
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if (VT == MVT::i32)
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return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
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X86::ESI, X86::EDI, X86::EBP, 0);
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else if (VT == MVT::i16)
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return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
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X86::SI, X86::DI, X86::BP, 0);
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else if (VT == MVT::i8)
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return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
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break;
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case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
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case 'Q': // Q_REGS
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return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0);
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if (VT == MVT::i32)
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return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
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else if (VT == MVT::i16)
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return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
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else if (VT == MVT::i8)
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return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
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break;
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case 'x': // SSE_REGS if SSE1 allowed
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if (Subtarget->hasSSE1())
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return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
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