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Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2014-04-26 18:35:24 +00:00
parent 57d7597572
commit 80d8db7a1f
32 changed files with 451 additions and 606 deletions
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24
lib/Target/AArch64/AArch64ISelLowering.cpp
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@@ -1294,8 +1294,7 @@ AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
FuncInfo->setVariadicGPRSize(GPRSaveSize);
if (!MemOps.empty()) {
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
MemOps.size());
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
}
}
@@ -1488,8 +1487,7 @@ AArch64TargetLowering::LowerReturn(SDValue Chain,
if (Flag.getNode())
RetOps.push_back(Flag);
return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
&RetOps[0], RetOps.size());
return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other, RetOps);
}
unsigned AArch64TargetLowering::getByValTypeAlignment(Type *Ty) const {
@@ -1680,8 +1678,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
// other. Combining them with this TokenFactor notes that fact for the rest of
// the backend.
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
// Most of the rest of the instructions need to be glued together; we don't
// want assignments to actual registers used by a call to be rearranged by a
@@ -1751,10 +1748,10 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
if (IsTailCall) {
return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, Ops);
}
Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, Ops);
InFlag = Chain.getValue(1);
// Now we can reclaim the stack, just as well do it before working out where
@@ -1966,8 +1963,7 @@ SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
}
// Build a tokenfactor for all the chains.
return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
&ArgChains[0], ArgChains.size());
return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
}
static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
@@ -2592,8 +2588,7 @@ SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
Ops.push_back(Glue);
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
Ops.size());
Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, Ops);
Glue = Chain.getValue(1);
// After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
@@ -3286,8 +3281,7 @@ AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
VROffsAddr, MachinePointerInfo(SV, 28),
false, false, 0));
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
MemOps.size());
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
}
SDValue
@@ -4822,7 +4816,7 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Ops.push_back(N);
Ops.push_back(Op.getOperand(I));
Ops.push_back(DAG.getConstant(I, MVT::i64));
N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, &Ops[0], 3);
N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Ops);
}
}
return N;