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[SystemZ] Add support for sibling calls
This first cut is pretty conservative. The final argument register (R6) is call-saved, so we would need to make sure that the R6 argument to a sibling call is the same as the R6 argument to the calling function, which seems worth keeping as a separate patch. Saying that integer truncations are free means that we no longer use the extending instructions LGF and LLGF for spills in int-conv-09.ll and int-conv-10.ll. Instead we treat the registers as 64 bits wide and truncate them to 32-bits where necessary. I think it's unlikely we'd use LGF and LLGF for spills in other situations for the same reason, so I'm removing the tests rather than replacing them. The associated code is generic and applies to many more instructions than just LGF and LLGF, so there is no corresponding code removal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188669 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
parent
2063637fa7
commit
80f54784da
@ -35,10 +35,6 @@ performance measurements.
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--
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We don't support tail calls at present.
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--
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We don't support prefetching yet.
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--
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@ -420,8 +420,7 @@ void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
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SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
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// Skip the return instruction.
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assert(MBBI->getOpcode() == SystemZ::RET &&
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"Can only insert epilogue into returning blocks");
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assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
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uint64_t StackSize = getAllocatedStackSize(MF);
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if (ZFI->getLowSavedGPR()) {
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@ -305,6 +305,22 @@ bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
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return AM.Scale == 0 || AM.Scale == 1;
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}
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bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
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if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
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return false;
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unsigned FromBits = FromType->getPrimitiveSizeInBits();
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unsigned ToBits = ToType->getPrimitiveSizeInBits();
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return FromBits > ToBits;
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}
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bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
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if (!FromVT.isInteger() || !ToVT.isInteger())
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return false;
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unsigned FromBits = FromVT.getSizeInBits();
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unsigned ToBits = ToVT.getSizeInBits();
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return FromBits > ToBits;
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}
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//===----------------------------------------------------------------------===//
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// Inline asm support
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//===----------------------------------------------------------------------===//
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@ -527,6 +543,17 @@ LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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#include "SystemZGenCallingConv.inc"
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bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
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Type *ToType) const {
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return isTruncateFree(FromType, ToType);
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}
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bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
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if (!CI->isTailCall())
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return false;
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return true;
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}
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// Value is a value that has been passed to us in the location described by VA
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// (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
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// any loads onto Chain.
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@ -689,6 +716,23 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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return Chain;
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}
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static bool canUseSiblingCall(CCState ArgCCInfo,
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SmallVectorImpl<CCValAssign> &ArgLocs) {
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// Punt if there are any indirect or stack arguments, or if the call
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// needs the call-saved argument register R6.
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for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
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CCValAssign &VA = ArgLocs[I];
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if (VA.getLocInfo() == CCValAssign::Indirect)
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return false;
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if (!VA.isRegLoc())
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return false;
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unsigned Reg = VA.getLocReg();
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if (Reg == SystemZ::R6W || Reg == SystemZ::R6D)
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return false;
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}
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return true;
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}
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SDValue
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SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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@ -699,26 +743,29 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
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SDValue Chain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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bool &isTailCall = CLI.IsTailCall;
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bool &IsTailCall = CLI.IsTailCall;
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CallingConv::ID CallConv = CLI.CallConv;
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bool IsVarArg = CLI.IsVarArg;
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MachineFunction &MF = DAG.getMachineFunction();
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EVT PtrVT = getPointerTy();
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// SystemZ target does not yet support tail call optimization.
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isTailCall = false;
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// Analyze the operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
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ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
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// We don't support GuaranteedTailCallOpt, only automatically-detected
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// sibling calls.
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if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
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IsTailCall = false;
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = ArgCCInfo.getNextStackOffset();
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// Mark the start of the call.
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
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DL);
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if (!IsTailCall)
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
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DL);
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// Copy argument values to their designated locations.
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SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
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@ -767,22 +814,27 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
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Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes, chained and glued together.
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SDValue Glue;
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for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
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Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
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RegsToPass[I].second, Glue);
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Glue = Chain.getValue(1);
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}
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// Accept direct calls by converting symbolic call addresses to the
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// associated Target* opcodes.
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// associated Target* opcodes. Force %r1 to be used for indirect
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// tail calls.
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SDValue Glue;
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
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Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
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} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
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Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
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} else if (IsTailCall) {
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Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
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Glue = Chain.getValue(1);
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Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
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}
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// Build a sequence of copy-to-reg nodes, chained and glued together.
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for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
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Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
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RegsToPass[I].second, Glue);
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Glue = Chain.getValue(1);
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}
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// The first call operand is the chain and the second is the target address.
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@ -802,6 +854,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
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// Emit the call.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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if (IsTailCall)
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return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
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Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
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Glue = Chain.getValue(1);
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@ -1689,6 +1743,7 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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OPCODE(RET_FLAG);
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OPCODE(CALL);
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OPCODE(SIBCALL);
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OPCODE(PCREL_WRAPPER);
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OPCODE(CMP);
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OPCODE(UCMP);
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@ -32,6 +32,7 @@ namespace SystemZISD {
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// is the target address. The arguments start at operand 2.
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// There is an optional glue operand at the end.
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CALL,
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SIBCALL,
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// Wraps a TargetGlobalAddress that should be loaded using PC-relative
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// accesses (LARL). Operand 0 is the address.
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@ -155,6 +156,8 @@ public:
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LLVM_OVERRIDE;
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virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
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LLVM_OVERRIDE;
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virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE;
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virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE;
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virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
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virtual std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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@ -174,6 +177,8 @@ public:
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MachineBasicBlock *BB) const LLVM_OVERRIDE;
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virtual SDValue LowerOperation(SDValue Op,
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SelectionDAG &DAG) const LLVM_OVERRIDE;
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virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE;
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virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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@ -212,6 +212,16 @@ let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
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"basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
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}
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// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards
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// are argument registers and since branching to R0 is a no-op.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1, R1 = 15 in {
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def CallJG : InstRIL<0xC04, (outs), (ins pcrel32call:$I2),
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"jg\t$I2", [(z_sibcall pcrel32call:$I2)]>;
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let R2 = 1, Uses = [R1D] in
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def CallBR : InstRR<0x07, (outs), (ins), "br\t%r1", [(z_sibcall R1D)]>;
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}
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// Define the general form of the call instructions for the asm parser.
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// These instructions don't hard-code %r14 as the return address register.
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def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
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@ -82,6 +82,9 @@ def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
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def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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SDNPVariadic]>;
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def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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SDNPVariadic]>;
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def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
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def z_cmp : SDNode<"SystemZISD::CMP", SDT_ZCmp, [SDNPOutGlue]>;
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def z_ucmp : SDNode<"SystemZISD::UCMP", SDT_ZCmp, [SDNPOutGlue]>;
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125
test/CodeGen/SystemZ/call-03.ll
Normal file
125
test/CodeGen/SystemZ/call-03.ll
Normal file
@ -0,0 +1,125 @@
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; Test sibling calls.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare void @ok(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
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float %f4, double %f6)
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declare void @uses_r6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, i64 %r6)
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declare void @uses_indirect(fp128 %r2)
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declare void @uses_stack(float %f0, float %f2, float %f4, float %f6,
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float %stack)
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declare i32 @returns_i32()
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declare i64 @returns_i64()
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; Check the maximum number of arguments that we can pass and still use
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; a sibling call.
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define void @f1() {
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; CHECK-LABEL: f1:
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; CHECK-DAG: lzer %f0
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; CHECK-DAG: lzdr %f2
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; CHECK-DAG: lhi %r2, 1
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; CHECK-DAG: lhi %r3, 2
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; CHECK-DAG: lhi %r4, 3
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; CHECK-DAG: lghi %r5, 4
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; CHECK-DAG: {{ler %f4, %f0|lzer %f4}}
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; CHECK-DAG: {{ldr %f6, %f2|lzdr %f6}}
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; CHECK: jg ok@PLT
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tail call void @ok(i8 1, i16 2, i32 3, i64 4, float 0.0, double 0.0,
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float 0.0, double 0.0)
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ret void
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}
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; Check a call that uses %r6 to pass an argument. At the moment we don't
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; use sibling calls in that case.
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define void @f2() {
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; CHECK-LABEL: f2:
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; CHECK: brasl %r14, uses_r6@PLT
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; CHECK: br %r14
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tail call void @uses_r6(i8 1, i16 2, i32 3, i64 4, i64 5)
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ret void
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}
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; Check a call that passes indirect arguments. We can't use sibling
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; calls in that case.
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define void @f3() {
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; CHECK-LABEL: f3:
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; CHECK: brasl %r14, uses_indirect@PLT
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; CHECK: br %r14
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tail call void @uses_indirect(fp128 0xL00000000000000000000000000000000)
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ret void
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}
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; Check a call that uses direct stack arguments, which again prevents
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; sibling calls
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define void @f4() {
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; CHECK-LABEL: f4:
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; CHECK: brasl %r14, uses_stack@PLT
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; CHECK: br %r14
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tail call void @uses_stack(float 0.0, float 0.0, float 0.0, float 0.0,
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float 0.0)
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ret void
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}
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; Check an indirect call. In this case the only acceptable choice for
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; the target register is %r1.
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define void @f5(void(i32, i32, i32, i32) *%foo) {
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; CHECK-LABEL: f5:
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; CHECK: lgr %r1, %r2
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; CHECK-DAG: lhi %r2, 1
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; CHECK-DAG: lhi %r3, 2
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; CHECK-DAG: lhi %r4, 3
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; CHECK-DAG: lhi %r5, 4
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; CHECK: br %r1
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tail call void %foo(i32 1, i32 2, i32 3, i32 4)
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ret void
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}
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; Check an indirect call that will be forced into a call-saved GPR
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; (which should be %r13, the highest GPR not used for anything else).
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define void @f6(void(i32) *%foo) {
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; CHECK-LABEL: f6:
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; CHECK: stmg %r13, %r15, 104(%r15)
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; CHECK: lgr %r13, %r2
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; CHECK: brasl %r14, returns_i32
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; CHECK: lgr %r1, %r13
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; CHECK: lmg %r13, %r15, 264(%r15)
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; CHECK: br %r1
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%arg = call i32 @returns_i32()
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tail call void %foo(i32 %arg)
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ret void
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}
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; Test a function that returns a value.
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define i64 @f7() {
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; CHECK-LABEL: f7:
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; CHECK: jg returns_i64@PLT
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%res = tail call i64 @returns_i64()
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ret i64 %res
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}
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; Test a function that returns a value truncated from i64 to i32.
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define i32 @f8() {
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; CHECK-LABEL: f8:
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; CHECK: jg returns_i64@PLT
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%res = tail call i64 @returns_i64()
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%trunc = trunc i64 %res to i32
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ret i32 %trunc
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}
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; Test a function that returns a value truncated from i64 to i7.
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define i7 @f9() {
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; CHECK-LABEL: f9:
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; CHECK: jg returns_i64@PLT
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%res = tail call i64 @returns_i64()
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%trunc = trunc i64 %res to i7
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ret i7 %trunc
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}
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; Test a function that returns a value truncated from i32 to i8.
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define i8 @f10() {
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; CHECK-LABEL: f10:
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; CHECK: jg returns_i32@PLT
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%res = tail call i32 @returns_i32()
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%trunc = trunc i32 %res to i8
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ret i8 %trunc
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}
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@ -102,80 +102,3 @@ define i64 @f9(i64 %src, i64 %index) {
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%ext = sext i32 %word to i64
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ret i64 %ext
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}
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; Test a case where we spill the source of at least one LGFR. We want
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; to use LGF if possible.
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define void @f10(i64 *%ptr1, i32 *%ptr2) {
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; CHECK-LABEL: f10:
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; CHECK: lgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%val0 = load volatile i32 *%ptr2
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%val1 = load volatile i32 *%ptr2
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%val2 = load volatile i32 *%ptr2
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%val3 = load volatile i32 *%ptr2
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%val4 = load volatile i32 *%ptr2
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%val5 = load volatile i32 *%ptr2
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%val6 = load volatile i32 *%ptr2
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%val7 = load volatile i32 *%ptr2
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%val8 = load volatile i32 *%ptr2
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%val9 = load volatile i32 *%ptr2
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%val10 = load volatile i32 *%ptr2
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%val11 = load volatile i32 *%ptr2
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%val12 = load volatile i32 *%ptr2
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%val13 = load volatile i32 *%ptr2
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%val14 = load volatile i32 *%ptr2
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%val15 = load volatile i32 *%ptr2
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|
||||
%ext0 = sext i32 %val0 to i64
|
||||
%ext1 = sext i32 %val1 to i64
|
||||
%ext2 = sext i32 %val2 to i64
|
||||
%ext3 = sext i32 %val3 to i64
|
||||
%ext4 = sext i32 %val4 to i64
|
||||
%ext5 = sext i32 %val5 to i64
|
||||
%ext6 = sext i32 %val6 to i64
|
||||
%ext7 = sext i32 %val7 to i64
|
||||
%ext8 = sext i32 %val8 to i64
|
||||
%ext9 = sext i32 %val9 to i64
|
||||
%ext10 = sext i32 %val10 to i64
|
||||
%ext11 = sext i32 %val11 to i64
|
||||
%ext12 = sext i32 %val12 to i64
|
||||
%ext13 = sext i32 %val13 to i64
|
||||
%ext14 = sext i32 %val14 to i64
|
||||
%ext15 = sext i32 %val15 to i64
|
||||
|
||||
store volatile i32 %val0, i32 *%ptr2
|
||||
store volatile i32 %val1, i32 *%ptr2
|
||||
store volatile i32 %val2, i32 *%ptr2
|
||||
store volatile i32 %val3, i32 *%ptr2
|
||||
store volatile i32 %val4, i32 *%ptr2
|
||||
store volatile i32 %val5, i32 *%ptr2
|
||||
store volatile i32 %val6, i32 *%ptr2
|
||||
store volatile i32 %val7, i32 *%ptr2
|
||||
store volatile i32 %val8, i32 *%ptr2
|
||||
store volatile i32 %val9, i32 *%ptr2
|
||||
store volatile i32 %val10, i32 *%ptr2
|
||||
store volatile i32 %val11, i32 *%ptr2
|
||||
store volatile i32 %val12, i32 *%ptr2
|
||||
store volatile i32 %val13, i32 *%ptr2
|
||||
store volatile i32 %val14, i32 *%ptr2
|
||||
store volatile i32 %val15, i32 *%ptr2
|
||||
|
||||
store volatile i64 %ext0, i64 *%ptr1
|
||||
store volatile i64 %ext1, i64 *%ptr1
|
||||
store volatile i64 %ext2, i64 *%ptr1
|
||||
store volatile i64 %ext3, i64 *%ptr1
|
||||
store volatile i64 %ext4, i64 *%ptr1
|
||||
store volatile i64 %ext5, i64 *%ptr1
|
||||
store volatile i64 %ext6, i64 *%ptr1
|
||||
store volatile i64 %ext7, i64 *%ptr1
|
||||
store volatile i64 %ext8, i64 *%ptr1
|
||||
store volatile i64 %ext9, i64 *%ptr1
|
||||
store volatile i64 %ext10, i64 *%ptr1
|
||||
store volatile i64 %ext11, i64 *%ptr1
|
||||
store volatile i64 %ext12, i64 *%ptr1
|
||||
store volatile i64 %ext13, i64 *%ptr1
|
||||
store volatile i64 %ext14, i64 *%ptr1
|
||||
store volatile i64 %ext15, i64 *%ptr1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -111,80 +111,3 @@ define i64 @f10(i64 %src, i64 %index) {
|
||||
%ext = zext i32 %word to i64
|
||||
ret i64 %ext
|
||||
}
|
||||
|
||||
; Test a case where we spill the source of at least one LLGFR. We want
|
||||
; to use LLGF if possible.
|
||||
define void @f11(i64 *%ptr1, i32 *%ptr2) {
|
||||
; CHECK-LABEL: f11:
|
||||
; CHECK: llgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
|
||||
; CHECK: br %r14
|
||||
%val0 = load volatile i32 *%ptr2
|
||||
%val1 = load volatile i32 *%ptr2
|
||||
%val2 = load volatile i32 *%ptr2
|
||||
%val3 = load volatile i32 *%ptr2
|
||||
%val4 = load volatile i32 *%ptr2
|
||||
%val5 = load volatile i32 *%ptr2
|
||||
%val6 = load volatile i32 *%ptr2
|
||||
%val7 = load volatile i32 *%ptr2
|
||||
%val8 = load volatile i32 *%ptr2
|
||||
%val9 = load volatile i32 *%ptr2
|
||||
%val10 = load volatile i32 *%ptr2
|
||||
%val11 = load volatile i32 *%ptr2
|
||||
%val12 = load volatile i32 *%ptr2
|
||||
%val13 = load volatile i32 *%ptr2
|
||||
%val14 = load volatile i32 *%ptr2
|
||||
%val15 = load volatile i32 *%ptr2
|
||||
|
||||
%ext0 = zext i32 %val0 to i64
|
||||
%ext1 = zext i32 %val1 to i64
|
||||
%ext2 = zext i32 %val2 to i64
|
||||
%ext3 = zext i32 %val3 to i64
|
||||
%ext4 = zext i32 %val4 to i64
|
||||
%ext5 = zext i32 %val5 to i64
|
||||
%ext6 = zext i32 %val6 to i64
|
||||
%ext7 = zext i32 %val7 to i64
|
||||
%ext8 = zext i32 %val8 to i64
|
||||
%ext9 = zext i32 %val9 to i64
|
||||
%ext10 = zext i32 %val10 to i64
|
||||
%ext11 = zext i32 %val11 to i64
|
||||
%ext12 = zext i32 %val12 to i64
|
||||
%ext13 = zext i32 %val13 to i64
|
||||
%ext14 = zext i32 %val14 to i64
|
||||
%ext15 = zext i32 %val15 to i64
|
||||
|
||||
store volatile i32 %val0, i32 *%ptr2
|
||||
store volatile i32 %val1, i32 *%ptr2
|
||||
store volatile i32 %val2, i32 *%ptr2
|
||||
store volatile i32 %val3, i32 *%ptr2
|
||||
store volatile i32 %val4, i32 *%ptr2
|
||||
store volatile i32 %val5, i32 *%ptr2
|
||||
store volatile i32 %val6, i32 *%ptr2
|
||||
store volatile i32 %val7, i32 *%ptr2
|
||||
store volatile i32 %val8, i32 *%ptr2
|
||||
store volatile i32 %val9, i32 *%ptr2
|
||||
store volatile i32 %val10, i32 *%ptr2
|
||||
store volatile i32 %val11, i32 *%ptr2
|
||||
store volatile i32 %val12, i32 *%ptr2
|
||||
store volatile i32 %val13, i32 *%ptr2
|
||||
store volatile i32 %val14, i32 *%ptr2
|
||||
store volatile i32 %val15, i32 *%ptr2
|
||||
|
||||
store volatile i64 %ext0, i64 *%ptr1
|
||||
store volatile i64 %ext1, i64 *%ptr1
|
||||
store volatile i64 %ext2, i64 *%ptr1
|
||||
store volatile i64 %ext3, i64 *%ptr1
|
||||
store volatile i64 %ext4, i64 *%ptr1
|
||||
store volatile i64 %ext5, i64 *%ptr1
|
||||
store volatile i64 %ext6, i64 *%ptr1
|
||||
store volatile i64 %ext7, i64 *%ptr1
|
||||
store volatile i64 %ext8, i64 *%ptr1
|
||||
store volatile i64 %ext9, i64 *%ptr1
|
||||
store volatile i64 %ext10, i64 *%ptr1
|
||||
store volatile i64 %ext11, i64 *%ptr1
|
||||
store volatile i64 %ext12, i64 *%ptr1
|
||||
store volatile i64 %ext13, i64 *%ptr1
|
||||
store volatile i64 %ext14, i64 *%ptr1
|
||||
store volatile i64 %ext15, i64 *%ptr1
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user