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Hexagon: Replace switch-case in isDotNewInst with TSFlags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178281 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
b52980be07
commit
810848d5b3
@ -1881,6 +1881,13 @@ bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
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return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
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}
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bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
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const uint64_t F = MI->getDesc().TSFlags;
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assert(isPredicated(MI));
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return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
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}
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bool
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HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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@ -2353,6 +2360,13 @@ isConditionalStore (const MachineInstr* MI) const {
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}
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}
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// Returns true, if any one of the operands is a dot new
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// insn, whether it is predicated dot new or register dot new.
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bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
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return (isNewValueInst(MI) ||
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(isPredicated(MI) && isPredicatedNew(MI)));
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}
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unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
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const uint64_t F = MI->getDesc().TSFlags;
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@ -127,6 +127,7 @@ public:
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const BranchProbability &Probability) const;
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virtual bool isPredicated(const MachineInstr *MI) const;
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virtual bool isPredicatedNew(const MachineInstr *MI) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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virtual bool
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@ -170,6 +171,7 @@ public:
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bool isConditionalLoad (const MachineInstr* MI) const;
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bool isConditionalStore(const MachineInstr* MI) const;
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bool isNewValueInst(const MachineInstr* MI) const;
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bool isDotNewInst(const MachineInstr* MI) const;
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bool isDeallocRet(const MachineInstr *MI) const;
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unsigned getInvertedPredicatedOpcode(const int Opc) const;
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bool isExtendable(const MachineInstr* MI) const;
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@ -508,29 +508,30 @@ def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
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//===----------------------------------------------------------------------===//
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// Conditional combine.
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let neverHasSideEffects = 1, isPredicated = 1 in
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let neverHasSideEffects = 1, isPredicated = 1 in {
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def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst = combine($src2, $src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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let isPredicatedFalse = 1 in
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def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst = combine($src2, $src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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let isPredicatedNew = 1 in
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def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1.new) $dst = combine($src2, $src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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let isPredicatedNew = 1, isPredicatedFalse = 1 in
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def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1.new) $dst = combine($src2, $src3)",
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[]>;
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}
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// Compare.
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defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
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@ -149,7 +149,6 @@ namespace {
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bool canReserveResourcesForConstExt(MachineInstr *MI);
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void reserveResourcesForConstExt(MachineInstr* MI);
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bool isNewValueInst(MachineInstr* MI);
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bool isDotNewInst(MachineInstr* MI);
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};
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}
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@ -2154,172 +2153,6 @@ static bool GetPredicateSense(MachineInstr* MI,
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return false;
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}
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bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
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const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
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if (QII->isNewValueInst(MI))
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return true;
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switch (MI->getOpcode()) {
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case Hexagon::TFR_cdnNotPt:
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case Hexagon::TFR_cdnPt:
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case Hexagon::TFRI_cdnNotPt:
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case Hexagon::TFRI_cdnPt:
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case Hexagon::LDrid_cdnPt :
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case Hexagon::LDrid_cdnNotPt :
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case Hexagon::LDrid_indexed_cdnPt :
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case Hexagon::LDrid_indexed_cdnNotPt :
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case Hexagon::POST_LDrid_cdnPt_V4 :
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case Hexagon::POST_LDrid_cdnNotPt_V4 :
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case Hexagon::LDriw_cdnPt :
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case Hexagon::LDriw_cdnNotPt :
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case Hexagon::LDriw_indexed_cdnPt :
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case Hexagon::LDriw_indexed_cdnNotPt :
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case Hexagon::POST_LDriw_cdnPt_V4 :
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case Hexagon::POST_LDriw_cdnNotPt_V4 :
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case Hexagon::LDrih_cdnPt :
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case Hexagon::LDrih_cdnNotPt :
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case Hexagon::LDrih_indexed_cdnPt :
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case Hexagon::LDrih_indexed_cdnNotPt :
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case Hexagon::POST_LDrih_cdnPt_V4 :
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case Hexagon::POST_LDrih_cdnNotPt_V4 :
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case Hexagon::LDrib_cdnPt :
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case Hexagon::LDrib_cdnNotPt :
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case Hexagon::LDrib_indexed_cdnPt :
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case Hexagon::LDrib_indexed_cdnNotPt :
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case Hexagon::POST_LDrib_cdnPt_V4 :
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case Hexagon::POST_LDrib_cdnNotPt_V4 :
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case Hexagon::LDriuh_cdnPt :
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case Hexagon::LDriuh_cdnNotPt :
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case Hexagon::LDriuh_indexed_cdnPt :
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case Hexagon::LDriuh_indexed_cdnNotPt :
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case Hexagon::POST_LDriuh_cdnPt_V4 :
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case Hexagon::POST_LDriuh_cdnNotPt_V4 :
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case Hexagon::LDriub_cdnPt :
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case Hexagon::LDriub_cdnNotPt :
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case Hexagon::LDriub_indexed_cdnPt :
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case Hexagon::LDriub_indexed_cdnNotPt :
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case Hexagon::POST_LDriub_cdnPt_V4 :
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case Hexagon::POST_LDriub_cdnNotPt_V4 :
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case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
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case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
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case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
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case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
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case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
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case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
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case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
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case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
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case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
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case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
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case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
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case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
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// Coditional add
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case Hexagon::ADD_ri_cdnPt:
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case Hexagon::ADD_ri_cdnNotPt:
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case Hexagon::ADD_rr_cdnPt:
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case Hexagon::ADD_rr_cdnNotPt:
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// Conditional logical operations
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case Hexagon::XOR_rr_cdnPt :
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case Hexagon::XOR_rr_cdnNotPt :
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case Hexagon::AND_rr_cdnPt :
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case Hexagon::AND_rr_cdnNotPt :
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case Hexagon::OR_rr_cdnPt :
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case Hexagon::OR_rr_cdnNotPt :
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// Conditonal subtract
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case Hexagon::SUB_rr_cdnPt :
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case Hexagon::SUB_rr_cdnNotPt :
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// Conditional combine
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case Hexagon::COMBINE_rr_cdnPt :
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case Hexagon::COMBINE_rr_cdnNotPt :
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// Conditional shift operations
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case Hexagon::ASLH_cdnPt_V4:
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case Hexagon::ASLH_cdnNotPt_V4:
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case Hexagon::ASRH_cdnPt_V4:
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case Hexagon::ASRH_cdnNotPt_V4:
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case Hexagon::SXTB_cdnPt_V4:
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case Hexagon::SXTB_cdnNotPt_V4:
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case Hexagon::SXTH_cdnPt_V4:
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case Hexagon::SXTH_cdnNotPt_V4:
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case Hexagon::ZXTB_cdnPt_V4:
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case Hexagon::ZXTB_cdnNotPt_V4:
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case Hexagon::ZXTH_cdnPt_V4:
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case Hexagon::ZXTH_cdnNotPt_V4:
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// Conditional stores
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case Hexagon::STrib_imm_cdnPt_V4 :
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case Hexagon::STrib_imm_cdnNotPt_V4 :
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case Hexagon::STrib_cdnPt_V4 :
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case Hexagon::STrib_cdnNotPt_V4 :
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case Hexagon::STrib_indexed_cdnPt_V4 :
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case Hexagon::STrib_indexed_cdnNotPt_V4 :
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case Hexagon::POST_STbri_cdnPt_V4 :
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case Hexagon::POST_STbri_cdnNotPt_V4 :
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case Hexagon::STrib_indexed_shl_cdnPt_V4 :
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case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
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// Store doubleword conditionally
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case Hexagon::STrid_indexed_cdnPt_V4 :
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case Hexagon::STrid_indexed_cdnNotPt_V4 :
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case Hexagon::STrid_indexed_shl_cdnPt_V4 :
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case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
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case Hexagon::POST_STdri_cdnPt_V4 :
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case Hexagon::POST_STdri_cdnNotPt_V4 :
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// Store halfword conditionally
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case Hexagon::STrih_cdnPt_V4 :
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case Hexagon::STrih_cdnNotPt_V4 :
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case Hexagon::STrih_indexed_cdnPt_V4 :
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case Hexagon::STrih_indexed_cdnNotPt_V4 :
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case Hexagon::STrih_imm_cdnPt_V4 :
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case Hexagon::STrih_imm_cdnNotPt_V4 :
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case Hexagon::STrih_indexed_shl_cdnPt_V4 :
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case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
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case Hexagon::POST_SThri_cdnPt_V4 :
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case Hexagon::POST_SThri_cdnNotPt_V4 :
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// Store word conditionally
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case Hexagon::STriw_cdnPt_V4 :
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case Hexagon::STriw_cdnNotPt_V4 :
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case Hexagon::STriw_indexed_cdnPt_V4 :
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case Hexagon::STriw_indexed_cdnNotPt_V4 :
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case Hexagon::STriw_imm_cdnPt_V4 :
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case Hexagon::STriw_imm_cdnNotPt_V4 :
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case Hexagon::STriw_indexed_shl_cdnPt_V4 :
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case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
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case Hexagon::POST_STwri_cdnPt_V4 :
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case Hexagon::POST_STwri_cdnNotPt_V4 :
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case Hexagon::LDd_GP_cdnPt_V4:
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case Hexagon::LDd_GP_cdnNotPt_V4:
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case Hexagon::LDb_GP_cdnPt_V4:
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case Hexagon::LDb_GP_cdnNotPt_V4:
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case Hexagon::LDub_GP_cdnPt_V4:
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case Hexagon::LDub_GP_cdnNotPt_V4:
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case Hexagon::LDh_GP_cdnPt_V4:
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case Hexagon::LDh_GP_cdnNotPt_V4:
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case Hexagon::LDuh_GP_cdnPt_V4:
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case Hexagon::LDuh_GP_cdnNotPt_V4:
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case Hexagon::LDw_GP_cdnPt_V4:
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case Hexagon::LDw_GP_cdnNotPt_V4:
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case Hexagon::STd_GP_cdnPt_V4:
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case Hexagon::STd_GP_cdnNotPt_V4:
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case Hexagon::STb_GP_cdnPt_V4:
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case Hexagon::STb_GP_cdnNotPt_V4:
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case Hexagon::STh_GP_cdnPt_V4:
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case Hexagon::STh_GP_cdnNotPt_V4:
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case Hexagon::STw_GP_cdnPt_V4:
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case Hexagon::STw_GP_cdnNotPt_V4:
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return true;
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}
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return false;
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}
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static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
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const HexagonInstrInfo *QII) {
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assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
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@ -2490,7 +2323,7 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
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// sense, i.e, either both should be negated or both should be none negated.
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if (( predRegNumDst != predRegNumSrc) ||
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isDotNewInst(PacketMI) != isDotNewInst(MI) ||
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QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
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GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
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return false;
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}
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@ -2600,8 +2433,9 @@ bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
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MachineBasicBlock::iterator &MII,
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const TargetRegisterClass* RC )
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{
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// already a dot new instruction
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if (isDotNewInst(MI) && !IsNewifyStore(MI))
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const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
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// Already a dot new instruction.
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if (QII->isDotNewInst(MI) && !IsNewifyStore(MI))
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return false;
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if (!isNewifiable(MI))
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@ -2616,7 +2450,6 @@ bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
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else {
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// Create a dot new machine instruction to see if resources can be
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// allocated. If not, bail out now.
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const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
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int NewOpcode = GetDotNewOp(MI->getOpcode());
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const MCInstrDesc &desc = QII->get(NewOpcode);
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DebugLoc dl;
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@ -2759,7 +2592,7 @@ bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
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// !p0 is not complimentary to p0.new
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return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
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(GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
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(isDotNewInst(MI1) == isDotNewInst(MI2)));
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(QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
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}
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// initPacketizerState - Initialize packetizer flags
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