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Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."

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This reverts commit r192352. It broke the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2013-10-10 15:15:17 +00:00
parent d622bef31d
commit 812ddcc50f
15 changed files with 3 additions and 2808 deletions
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53
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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@@ -361,59 +361,6 @@ DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo,
unsigned RegID,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
uint16_t Register = getReg(Decoder, RegID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Register));
return MCDisassembler::Success;
}
static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID,
Decoder);
}
static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID,
Decoder);
}
static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
unsigned RegNo, uint64_t Address,
const void *Decoder) {
return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID,
Decoder);
}
static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
unsigned RegNo, uint64_t Address,
const void *Decoder) {
return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID,
Decoder);
}
static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID,
Decoder);
}
static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID,
Decoder);
}
static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
unsigned OptionHiS,
uint64_t Address,