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Use the BuildMI overload that sets up a destination register

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instead of the one that doesn't and then adding it manually.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55006 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-08-19 20:46:54 +00:00
parent 32155acb8a
commit 8133a52eb5
1 changed files with 3 additions and 6 deletions
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9
lib/CodeGen/SelectionDAG/FastISel.cpp
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@ -70,10 +70,9 @@ unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
const TargetRegisterClass* RC) { const TargetRegisterClass* RC) {
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode); const TargetInstrDesc &II = TII->get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II);
unsigned ResultReg = MRI.createVirtualRegister(RC); unsigned ResultReg = MRI.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(ResultReg, true)); MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MBB->push_back(MI); MBB->push_back(MI);
return ResultReg; return ResultReg;
@ -84,10 +83,9 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
unsigned Op0) { unsigned Op0) {
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode); const TargetInstrDesc &II = TII->get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II);
unsigned ResultReg = MRI.createVirtualRegister(RC); unsigned ResultReg = MRI.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(ResultReg, true)); MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MI->addOperand(MachineOperand::CreateReg(Op0, false)); MI->addOperand(MachineOperand::CreateReg(Op0, false));
MBB->push_back(MI); MBB->push_back(MI);
@ -99,10 +97,9 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
unsigned Op0, unsigned Op1) { unsigned Op0, unsigned Op1) {
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode); const TargetInstrDesc &II = TII->get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II);
unsigned ResultReg = MRI.createVirtualRegister(RC); unsigned ResultReg = MRI.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(ResultReg, true)); MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MI->addOperand(MachineOperand::CreateReg(Op0, false)); MI->addOperand(MachineOperand::CreateReg(Op0, false));
MI->addOperand(MachineOperand::CreateReg(Op1, false)); MI->addOperand(MachineOperand::CreateReg(Op1, false));