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Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -101,7 +101,9 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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// A8.6.123 PUSH
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// A8.6.123 PUSH
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if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
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if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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MI->getOperand(0).getReg() == ARM::SP &&
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MI->getNumOperands() > 5) {
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// Should only print PUSH if there are at least two registers in the list.
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O << '\t' << "push";
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O << '\t' << "push";
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printPredicateOperand(MI, 2, O);
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printPredicateOperand(MI, 2, O);
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if (Opcode == ARM::t2STMDB_UPD)
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if (Opcode == ARM::t2STMDB_UPD)
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@ -122,7 +124,9 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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// A8.6.122 POP
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// A8.6.122 POP
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if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
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if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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MI->getOperand(0).getReg() == ARM::SP &&
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MI->getNumOperands() > 5) {
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// Should only print POP if there are at least two registers in the list.
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O << '\t' << "pop";
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O << '\t' << "pop";
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printPredicateOperand(MI, 2, O);
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printPredicateOperand(MI, 2, O);
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if (Opcode == ARM::t2LDMIA_UPD)
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if (Opcode == ARM::t2LDMIA_UPD)
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@ -317,3 +317,7 @@
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# CHECK: stc2l p0, c0, [r2], #-96
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# CHECK: stc2l p0, c0, [r2], #-96
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0x18 0x0 0x62 0xfc
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0x18 0x0 0x62 0xfc
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# CHECK: ldmgt sp!, {r9}
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0x00 0x02 0xbd 0xc8
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