mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-01 12:24:24 +00:00
Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
@ -254,7 +254,6 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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.addReg(Base, getKillRegState(BaseKill))
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.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
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.addImm(Pred).addReg(PredReg);
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MIB.addReg(0); // Add optional writeback (0 for now).
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for (unsigned i = 0; i != NumRegs; ++i)
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MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
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| getKillRegState(Regs[i].second));
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@ -443,7 +442,7 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
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case ARM::STM:
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case ARM::t2LDM:
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case ARM::t2STM:
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return (MI->getNumOperands() - 5) * 4;
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return (MI->getNumOperands() - 4) * 4;
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case ARM::VLDMS:
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case ARM::VSTMS:
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case ARM::VLDMD:
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@ -452,6 +451,21 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
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}
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}
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static unsigned getUpdatingLSMultipleOpcode(unsigned Opc) {
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switch (Opc) {
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case ARM::LDM: return ARM::LDM_UPD;
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case ARM::STM: return ARM::STM_UPD;
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case ARM::t2LDM: return ARM::t2LDM_UPD;
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case ARM::t2STM: return ARM::t2STM_UPD;
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case ARM::VLDMS: return ARM::VLDMS_UPD;
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case ARM::VLDMD: return ARM::VLDMD_UPD;
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case ARM::VSTMS: return ARM::VSTMS_UPD;
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case ARM::VSTMD: return ARM::VSTMD_UPD;
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default: llvm_unreachable("Unhandled opcode!");
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}
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return 0;
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}
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/// MergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base
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/// register into the LDM/STM/VLDM{D|S}/VSTM{D|S} op when possible:
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///
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@ -470,117 +484,119 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = MBBI;
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unsigned Base = MI->getOperand(0).getReg();
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bool BaseKill = MI->getOperand(0).isKill();
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unsigned Bytes = getLSMultipleTransferSize(MI);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
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int Opcode = MI->getOpcode();
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DebugLoc dl = MI->getDebugLoc();
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bool isAM4 = (Opcode == ARM::LDM || Opcode == ARM::t2LDM ||
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Opcode == ARM::STM || Opcode == ARM::t2STM);
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if (isAM4) {
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if (ARM_AM::getAM4WBFlag(MI->getOperand(1).getImm()))
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return false;
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bool DoMerge = false;
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ARM_AM::AMSubMode Mode = ARM_AM::ia;
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unsigned Offset = 0;
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// Can't use the updating AM4 sub-mode if the base register is also a dest
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if (isAM4) {
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// Can't use an updating ld/st if the base register is also a dest
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// register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
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for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i) {
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if (MI->getOperand(i).getReg() == Base)
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return false;
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}
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ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
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if (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
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if (Mode == ARM_AM::ia &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
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MI->getOperand(4).setReg(Base);
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MI->getOperand(4).setIsDef();
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MBB.erase(PrevMBBI);
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return true;
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} else if (Mode == ARM_AM::ib &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
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MI->getOperand(4).setReg(Base); // WB to base
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MI->getOperand(4).setIsDef();
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MBB.erase(PrevMBBI);
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return true;
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}
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}
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if (MBBI != MBB.end()) {
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MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
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if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
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isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
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MI->getOperand(4).setReg(Base); // WB to base
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MI->getOperand(4).setIsDef();
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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return true;
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} else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
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isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
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MI->getOperand(4).setReg(Base); // WB to base
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MI->getOperand(4).setIsDef();
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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return true;
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}
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}
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assert(!ARM_AM::getAM4WBFlag(MI->getOperand(1).getImm()));
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Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
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} else {
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// VLDM{D|S}, VSTM{D|S} addressing mode 5 ops.
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if (ARM_AM::getAM5WBFlag(MI->getOperand(1).getImm()))
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return false;
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assert(!ARM_AM::getAM5WBFlag(MI->getOperand(1).getImm()));
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Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
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Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
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}
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ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
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unsigned Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
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if (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
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// Try merging with the previous instruction.
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if (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
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if (isAM4) {
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if (Mode == ARM_AM::ia &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
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MI->getOperand(4).setReg(Base); // WB to base
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MI->getOperand(4).setIsDef();
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MBB.erase(PrevMBBI);
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return true;
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DoMerge = true;
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Mode = ARM_AM::db;
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} else if (isAM4 && Mode == ARM_AM::ib &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
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DoMerge = true;
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Mode = ARM_AM::da;
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}
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} else {
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if (Mode == ARM_AM::ia &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
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Mode = ARM_AM::db;
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DoMerge = true;
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}
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}
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if (DoMerge)
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MBB.erase(PrevMBBI);
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}
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if (MBBI != MBB.end()) {
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MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
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// Try merging with the next instruction.
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if (!DoMerge && MBBI != MBB.end()) {
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MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI);
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if (isAM4) {
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if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
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isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
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DoMerge = true;
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} else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
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isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
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DoMerge = true;
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}
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} else {
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if (Mode == ARM_AM::ia &&
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isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
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MI->getOperand(4).setReg(Base); // WB to base
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MI->getOperand(4).setIsDef();
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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DoMerge = true;
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}
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return true;
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}
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if (DoMerge) {
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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}
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}
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return false;
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if (!DoMerge)
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return false;
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unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode);
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
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.addReg(Base, getDefRegState(true)) // WB base register
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.addReg(Base, getKillRegState(BaseKill));
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if (isAM4) {
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// [t2]LDM_UPD, [t2]STM_UPD
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MIB.addImm(ARM_AM::getAM4ModeImm(Mode, true))
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.addImm(Pred).addReg(PredReg);
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} else {
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// VLDM[SD}_UPD, VSTM[SD]_UPD
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MIB.addImm(ARM_AM::getAM5Opc(Mode, true, Offset))
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.addImm(Pred).addReg(PredReg);
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}
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// Transfer the rest of operands.
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for (unsigned OpNum = 4, e = MI->getNumOperands(); OpNum != e; ++OpNum)
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MIB.addOperand(MI->getOperand(OpNum));
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// Transfer memoperands.
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(*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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MBB.erase(MBBI);
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return true;
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}
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static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
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switch (Opc) {
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case ARM::LDR: return ARM::LDR_PRE;
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case ARM::STR: return ARM::STR_PRE;
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case ARM::VLDRS: return ARM::VLDMS;
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case ARM::VLDRD: return ARM::VLDMD;
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case ARM::VSTRS: return ARM::VSTMS;
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case ARM::VSTRD: return ARM::VSTMD;
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case ARM::VLDRS: return ARM::VLDMS_UPD;
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case ARM::VLDRD: return ARM::VLDMD_UPD;
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case ARM::VSTRS: return ARM::VSTMS_UPD;
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case ARM::VSTRD: return ARM::VSTMD_UPD;
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case ARM::t2LDRi8:
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case ARM::t2LDRi12:
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return ARM::t2LDR_PRE;
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@ -596,10 +612,10 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
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switch (Opc) {
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case ARM::LDR: return ARM::LDR_POST;
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case ARM::STR: return ARM::STR_POST;
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case ARM::VLDRS: return ARM::VLDMS;
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case ARM::VLDRD: return ARM::VLDMD;
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case ARM::VSTRS: return ARM::VSTMS;
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case ARM::VSTRD: return ARM::VSTMD;
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case ARM::VLDRS: return ARM::VLDMS_UPD;
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case ARM::VLDRD: return ARM::VLDMD_UPD;
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case ARM::VSTRS: return ARM::VSTMS_UPD;
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case ARM::VSTRD: return ARM::VSTMD_UPD;
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case ARM::t2LDRi8:
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case ARM::t2LDRi12:
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return ARM::t2LDR_POST;
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@ -699,13 +715,13 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
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if (isAM5) {
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// VLDM[SD}, VSTM[SD]
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// VLDM[SD}_UPD, VSTM[SD]_UPD
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MachineOperand &MO = MI->getOperand(0);
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BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
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.addReg(Base, getDefRegState(true)) // WB base register
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.addReg(Base, getKillRegState(isLd ? BaseKill : false))
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.addImm(Offset)
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.addImm(Pred).addReg(PredReg)
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.addReg(Base, getDefRegState(true)) // WB base register
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.addReg(MO.getReg(), (isLd ? getDefRegState(true) :
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getKillRegState(MO.isKill())));
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} else if (isLd) {
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@ -909,7 +925,6 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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.addReg(BaseReg, getKillRegState(BaseKill))
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.addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
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.addImm(Pred).addReg(PredReg)
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.addReg(0)
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.addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
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.addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
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++NumLDRD2LDM;
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@ -918,7 +933,6 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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.addReg(BaseReg, getKillRegState(BaseKill))
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.addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
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.addImm(Pred).addReg(PredReg)
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.addReg(0)
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.addReg(EvenReg,
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getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
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.addReg(OddReg,
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@ -1156,7 +1170,8 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
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if (MBBI != MBB.begin() &&
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(MBBI->getOpcode() == ARM::BX_RET || MBBI->getOpcode() == ARM::tBX_RET)) {
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MachineInstr *PrevMI = prior(MBBI);
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if (PrevMI->getOpcode() == ARM::LDM || PrevMI->getOpcode() == ARM::t2LDM) {
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if (PrevMI->getOpcode() == ARM::LDM_UPD ||
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PrevMI->getOpcode() == ARM::t2LDM_UPD) {
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MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1);
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if (MO.getReg() != ARM::LR)
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return false;
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