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[X86] Improve the selection of SSE3/AVX addsub instructions.
This patch teaches the backend how to canonicalize a shuffle vectors
according to the rule:
- (shuffle (FADD A, B), (FSUB A, B), Mask) ->
(shuffle (FSUB A, -B), (FADD A, -B), Mask)
Where 'Mask' is:
<0,5,2,7> ;; for v4f32 and v4f64 shuffles.
<0,3> ;; for v2f64 shuffles.
<0,9,2,11,4,13,6,15> ;; for v8f32 shuffles.
In general, ISel only knows how to pattern-match a canonical
'fadd + fsub + blendi' dag node sequence into an ADDSUB instruction.
This new rule allows to convert a non-canonical dag sequence into a
canonical one that will be matched by a single ADDSUB at ISel stage.
The idea of converting a non-canonical ADDSUB into a canonical one by
swapping the first two operands of the shuffle, and then negating the
second operand of the FADD and FSUB, was originally proposed by Hal Finkel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211771 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
c2b11baf5f
commit
817812f61c
@ -18014,6 +18014,49 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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SDValue N1 = N->getOperand(1);
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EVT VT = N->getValueType(0);
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// Canonicalize shuffles that perform 'addsub' on packed float vectors
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// according to the rule:
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// (shuffle (FADD A, B), (FSUB A, B), Mask) ->
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// (shuffle (FSUB A, -B), (FADD A, -B), Mask)
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//
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// Where 'Mask' is:
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// <0,5,2,7> -- for v4f32 and v4f64 shuffles;
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// <0,3> -- for v2f64 shuffles;
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// <0,9,2,11,4,13,6,15> -- for v8f32 shuffles.
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//
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// This helps pattern-matching more SSE3/AVX ADDSUB instructions
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// during ISel stage.
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if (N->getOpcode() == ISD::VECTOR_SHUFFLE &&
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((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
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(Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
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N0->getOpcode() == ISD::FADD && N1->getOpcode() == ISD::FSUB &&
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// Operands to the FADD and FSUB must be the same.
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((N0->getOperand(0) == N1->getOperand(0) &&
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N0->getOperand(1) == N1->getOperand(1)) ||
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// FADD is commutable. See if by commuting the operands of the FADD
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// we would still be able to match the operands of the FSUB dag node.
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(N0->getOperand(1) == N1->getOperand(0) &&
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N0->getOperand(0) == N1->getOperand(1))) &&
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N0->getOperand(0)->getOpcode() != ISD::UNDEF &&
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N0->getOperand(1)->getOpcode() != ISD::UNDEF) {
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ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
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unsigned NumElts = VT.getVectorNumElements();
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ArrayRef<int> Mask = SV->getMask();
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bool CanFold = true;
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for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i)
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CanFold = Mask[i] == (i & 1) ? i + NumElts : i;
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if (CanFold) {
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SDValue Op0 = N1->getOperand(0);
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SDValue Op1 = DAG.getNode(ISD::FNEG, dl, VT, N1->getOperand(1));
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SDValue Sub = DAG.getNode(ISD::FSUB, dl, VT, Op0, Op1);
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SDValue Add = DAG.getNode(ISD::FADD, dl, VT, Op0, Op1);
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return DAG.getVectorShuffle(VT, dl, Sub, Add, Mask);
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}
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}
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// Don't create instructions with illegal types after legalize types has run.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
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@ -3,7 +3,7 @@
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; Test ADDSUB ISel patterns.
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; All the functions below are obtained from the following source:
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; Functions below are obtained from the following source:
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;
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; typedef double double2 __attribute__((ext_vector_type(2)));
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; typedef double double4 __attribute__((ext_vector_type(4)));
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@ -19,7 +19,7 @@
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; float8 test2(float8 A, float8 B) {
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; float8 X = A - B;
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; float8 Y = A + B;
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; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], [7]};
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; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], Y[7]};
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; }
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;
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; double4 test3(double4 A, double4 B) {
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@ -141,3 +141,156 @@ define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
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; AVX: vaddsubpd
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; CHECK-NEXT: ret
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; Functions below are obtained from the following source:
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;
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; float4 test1(float4 A, float4 B) {
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; float4 X = A + B;
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; float4 Y = A - B;
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; return (float4){X[0], Y[1], X[2], Y[3]};
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; }
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;
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; float8 test2(float8 A, float8 B) {
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; float8 X = A + B;
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; float8 Y = A - B;
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; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], Y[7]};
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; }
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;
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; double4 test3(double4 A, double4 B) {
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; double4 X = A + B;
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; double4 Y = A - B;
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; return (double4){X[0], Y[1], X[2], Y[3]};
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; }
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;
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; double2 test4(double2 A, double2 B) {
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; double2 X = A + B;
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; double2 Y = A - B;
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; return (double2){X[0], Y[1]};
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; }
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define <4 x float> @test5(<4 x float> %A, <4 x float> %B) {
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%sub = fsub <4 x float> %A, %B
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%add = fadd <4 x float> %A, %B
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%vecinit6 = shufflevector <4 x float> %add, <4 x float> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %vecinit6
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}
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; CHECK-LABEL: test5
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; SSE: xorps
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; SSE-NEXT: addsubps
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; AVX: vxorps
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; AVX-NEXT: vaddsubps
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; CHECK: ret
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define <8 x float> @test6(<8 x float> %A, <8 x float> %B) {
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%sub = fsub <8 x float> %A, %B
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%add = fadd <8 x float> %A, %B
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%vecinit14 = shufflevector <8 x float> %add, <8 x float> %sub, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x float> %vecinit14
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}
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; CHECK-LABEL: test6
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; SSE: xorps
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; SSE-NEXT: addsubps
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; SSE: xorps
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; SSE-NEXT: addsubps
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; AVX: vxorps
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; AVX-NEXT: vaddsubps
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; AVX-NOT: vxorps
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; AVX-NOT: vaddsubps
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; CHECK: ret
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define <4 x double> @test7(<4 x double> %A, <4 x double> %B) {
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%sub = fsub <4 x double> %A, %B
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%add = fadd <4 x double> %A, %B
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%vecinit6 = shufflevector <4 x double> %add, <4 x double> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x double> %vecinit6
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}
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; CHECK-LABEL: test7
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; SSE: xorpd
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; SSE-NEXT: addsubpd
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; SSE: xorpd
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; SSE-NEXT: addsubpd
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; AVX: vxorpd
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; AVX-NEXT: vaddsubpd
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; AVX-NOT: vxorpd
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; AVX-NOT: vaddsubpd
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; CHECK: ret
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define <2 x double> @test8(<2 x double> %A, <2 x double> %B) #0 {
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%add = fadd <2 x double> %A, %B
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%sub = fsub <2 x double> %A, %B
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%vecinit2 = shufflevector <2 x double> %add, <2 x double> %sub, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %vecinit2
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}
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; CHECK-LABEL: test8
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; SSE: xorpd
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; SSE-NEXT: addsubpd
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; AVX: vxorpd
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; AVX-NEXT: vaddsubpd
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; CHECK: ret
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define <4 x float> @test5b(<4 x float> %A, <4 x float> %B) {
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%sub = fsub <4 x float> %A, %B
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%add = fadd <4 x float> %B, %A
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%vecinit6 = shufflevector <4 x float> %add, <4 x float> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %vecinit6
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}
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; CHECK-LABEL: test5
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; SSE: xorps
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; SSE-NEXT: addsubps
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; AVX: vxorps
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; AVX-NEXT: vaddsubps
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; CHECK: ret
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define <8 x float> @test6b(<8 x float> %A, <8 x float> %B) {
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%sub = fsub <8 x float> %A, %B
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%add = fadd <8 x float> %B, %A
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%vecinit14 = shufflevector <8 x float> %add, <8 x float> %sub, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x float> %vecinit14
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}
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; CHECK-LABEL: test6
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; SSE: xorps
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; SSE-NEXT: addsubps
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; SSE: xorps
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; SSE-NEXT: addsubps
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; AVX: vxorps
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; AVX-NEXT: vaddsubps
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; AVX-NOT: vxorps
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; AVX-NOT: vaddsubps
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; CHECK: ret
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define <4 x double> @test7b(<4 x double> %A, <4 x double> %B) {
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%sub = fsub <4 x double> %A, %B
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%add = fadd <4 x double> %B, %A
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%vecinit6 = shufflevector <4 x double> %add, <4 x double> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x double> %vecinit6
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}
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; CHECK-LABEL: test7
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; SSE: xorpd
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; SSE-NEXT: addsubpd
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; SSE: xorpd
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; SSE-NEXT: addsubpd
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; AVX: vxorpd
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; AVX-NEXT: vaddsubpd
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; AVX-NOT: vxorpd
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; AVX-NOT: vaddsubpd
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; CHECK: ret
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define <2 x double> @test8b(<2 x double> %A, <2 x double> %B) #0 {
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%add = fadd <2 x double> %B, %A
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%sub = fsub <2 x double> %A, %B
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%vecinit2 = shufflevector <2 x double> %add, <2 x double> %sub, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %vecinit2
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}
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; CHECK-LABEL: test8
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; SSE: xorpd
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; SSE-NEXT: addsubpd
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; AVX: vxorpd
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; AVX-NEXT: vaddsubpd
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; CHECK: ret
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