6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-04 07:32:13 +00:00
Code Issues Projects Releases Wiki Activity

Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73898 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-06-22 20:49:32 +00:00
parent c236a345c7
commit 81909b7423
2 changed files with 50 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -739,6 +739,9 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
// After updating the operand, check if the machine instruction has
// become a copy. If so, update its val# information.
if (JoinedCopies.count(UseMI))
continue;
const TargetInstrDesc &TID = UseMI->getDesc();
unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
@ -749,9 +752,10 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
allocatableRegs_[CopyDstReg])) {
LiveInterval &LI = li_->getInterval(CopyDstReg);
unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx);
if (DLR->valno->def == DefIdx)
DLR->valno->copy = UseMI;
if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
if (DLR->valno->def == DefIdx)
DLR->valno->copy = UseMI;
}
}
}
}

43
test/CodeGen/ARM/2009-06-22-CoalescerBug.ll Normal file
View File

@ -0,0 +1,43 @@
; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin
%struct.rtunion = type { i64 }
%struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }
define arm_apcscc void @simplify_unary_real(i8* nocapture %p) nounwind {
entry:
%tmp121 = load i64* null, align 4 ; <i64> [#uses=1]
%0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1]
%tmp122 = load i64* %0, align 4 ; <i64> [#uses=1]
%1 = zext i64 undef to i192 ; <i192> [#uses=2]
%2 = zext i64 %tmp121 to i192 ; <i192> [#uses=1]
%3 = shl i192 %2, 64 ; <i192> [#uses=2]
%4 = zext i64 %tmp122 to i192 ; <i192> [#uses=1]
%5 = shl i192 %4, 128 ; <i192> [#uses=1]
%6 = or i192 %3, %1 ; <i192> [#uses=1]
%7 = or i192 %6, %5 ; <i192> [#uses=2]
switch i32 undef, label %bb82 [
i32 77, label %bb38
i32 129, label %bb21
i32 130, label %bb20
]
bb20: ; preds = %entry
ret void
bb21: ; preds = %entry
br i1 undef, label %bb82, label %bb29
bb29: ; preds = %bb21
%tmp18.i = and i192 %3, 1208907372870555465154560 ; <i192> [#uses=1]
%mask.i = or i192 %tmp18.i, %1 ; <i192> [#uses=1]
%mask41.i = or i192 %mask.i, 0 ; <i192> [#uses=1]
br label %bb82
bb38: ; preds = %entry
br label %bb82
bb82: ; preds = %bb38, %bb29, %bb21, %entry
%d.0 = phi i192 [ %mask41.i, %bb29 ], [ undef, %bb38 ], [ %7, %entry ], [ %7, %bb21 ] ; <i192> [#uses=1]
%tmp51 = trunc i192 %d.0 to i64 ; <i64> [#uses=0]
ret void
}