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Turn on post register allocation scheduler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153554 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-03-28 00:24:17 +00:00
parent 37ac18ef2f
commit 81a424b3c5
4 changed files with 22 additions and 0 deletions
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5
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -132,6 +132,11 @@ getReservedRegs(const MachineFunction &MF) const {
return Reserved; return Reserved;
} }
bool
MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
return true;
}
// This function eliminate ADJCALLSTACKDOWN, // This function eliminate ADJCALLSTACKDOWN,
// ADJCALLSTACKUP pseudo instructions // ADJCALLSTACKUP pseudo instructions
void MipsRegisterInfo:: void MipsRegisterInfo::

2
lib/Target/Mips/MipsRegisterInfo.h
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@ -47,6 +47,8 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
BitVector getReservedRegs(const MachineFunction &MF) const; BitVector getReservedRegs(const MachineFunction &MF) const;
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF, void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const; MachineBasicBlock::iterator I) const;

12
lib/Target/Mips/MipsSubtarget.cpp
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@ -13,6 +13,7 @@
#include "MipsSubtarget.h" #include "MipsSubtarget.h"
#include "Mips.h" #include "Mips.h"
#include "MipsRegisterInfo.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
#define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_TARGET_DESC
@ -54,3 +55,14 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
if (TT.find("linux") == std::string::npos) if (TT.find("linux") == std::string::npos)
IsLinux = false; IsLinux = false;
} }
bool
MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
CriticalPathRCs.clear();
CriticalPathRCs.push_back(hasMips64() ?
&Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass);
return OptLevel >= CodeGenOpt::Default;
}

3
lib/Target/Mips/MipsSubtarget.h
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@ -89,6 +89,9 @@ protected:
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
public: public:
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
/// Only O32 and EABI supported right now. /// Only O32 and EABI supported right now.
bool isABI_EABI() const { return MipsABI == EABI; } bool isABI_EABI() const { return MipsABI == EABI; }