6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-01 00:33:09 +00:00
Code Issues Projects Releases Wiki Activity

Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.

Browse Source 
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76889 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-23 18:26:03 +00:00
parent 6316fbcb04
commit 81c102ba66
2 changed files with 7 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
lib/Target/ARM/ARMInstrThumb.td
View File

@ -552,22 +552,11 @@ let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
// tLEApcrel - Load a pc-relative address into a register without offending the // tLEApcrel - Load a pc-relative address into a register without offending the
// assembler. // assembler.
let Defs = [CPSR] in { def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label),
def tLEApcrel : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label), "adr $dst, #$label", []>;
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("\tmovs $dst, #${:private}PCRELV${:uid}\n",
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
[]>;
def tLEApcrelJT : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id), def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}," "adr $dst, #${label}_${id:no_hash}", []>;
" (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("\tmovs $dst, #${:private}PCRELV${:uid}\n",
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
[]>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// TLS Instructions // TLS Instructions

15
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -450,20 +450,11 @@ def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
// LEApcrel - Load a pc-relative address into a register without offending the // LEApcrel - Load a pc-relative address into a register without offending the
// assembler. // assembler.
def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(", "adr$p $dst, #$label", []>;
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #${:private}PCRELV${:uid}")),
[]>;
def t2LEApcrelJT : T2XI<(outs GPR:$dst), def t2LEApcrelJT : T2XI<(outs GPR:$dst),
(ins i32imm:$label, i32imm:$id, pred:$p), (ins i32imm:$label, i32imm:$id, pred:$p),
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}," "adr$p $dst, #${label}_${id:no_hash}", []>;
" (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #${:private}PCRELV${:uid}")),
[]>;
// ADD rd, sp, #so_imm // ADD rd, sp, #so_imm
def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),